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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-21 22:53:05 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-23 23:49:36 -0800 |
| commit | 487f1b7cd8fc74e94ac76f8912ce8f3e335ba940 (patch) | |
| tree | 38f53a31dd7c57684dfc38ed18291bd8079c7271 /riscv/encoding.h | |
| parent | 15f84304187ca881f206cdf4e2dba9f706902013 (diff) | |
| download | spike-487f1b7cd8fc74e94ac76f8912ce8f3e335ba940.zip spike-487f1b7cd8fc74e94ac76f8912ce8f3e335ba940.tar.gz spike-487f1b7cd8fc74e94ac76f8912ce8f3e335ba940.tar.bz2 | |
rvv: rename sqrt/reciprocal instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 160dc29..ccc8d74 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in - * https://github.com/riscv/riscv-opcodes (c4d2cc0) + * https://github.com/riscv/riscv-opcodes (79c18f0) */ /* See LICENSE for license details. */ @@ -1584,10 +1584,10 @@ #define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f #define MATCH_VFSQRT_V 0x4c001057 #define MASK_VFSQRT_V 0xfc0ff07f -#define MATCH_VFRSQRTE7_V 0x4c021057 -#define MASK_VFRSQRTE7_V 0xfc0ff07f -#define MATCH_VFRECE7_V 0x4c029057 -#define MASK_VFRECE7_V 0xfc0ff07f +#define MATCH_VFRSQRT7_V 0x4c021057 +#define MASK_VFRSQRT7_V 0xfc0ff07f +#define MATCH_VFREC7_V 0x4c029057 +#define MASK_VFREC7_V 0xfc0ff07f #define MATCH_VFCLASS_V 0x4c081057 #define MASK_VFCLASS_V 0xfc0ff07f #define MATCH_VFWADD_VV 0xc0001057 @@ -3068,8 +3068,8 @@ DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) -DECLARE_INSN(vfrsqrte7_v, MATCH_VFRSQRTE7_V, MASK_VFRSQRTE7_V) -DECLARE_INSN(vfrece7_v, MATCH_VFRECE7_V, MASK_VFRECE7_V) +DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) +DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) |