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| author | Clifford Wolf <clifford@clifford.at> | 2019-12-05 17:27:14 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-10-22 17:00:11 -0700 |
| commit | 2622defd0cca6cc59a80227f5fa909926f44d42e (patch) | |
| tree | 7492d6b8ac4b093df336d5acf2703e851b29579b /riscv/encoding.h | |
| parent | 672c50ca1605949aaa82992746ba7011f571aa89 (diff) | |
| download | spike-2622defd0cca6cc59a80227f5fa909926f44d42e.zip spike-2622defd0cca6cc59a80227f5fa909926f44d42e.tar.gz spike-2622defd0cca6cc59a80227f5fa909926f44d42e.tar.bz2 | |
[riscv-bitmanip] Add sh[123]add[u.w] instruction
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 6654183..158a622 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -524,6 +524,12 @@ #define MASK_CRC32C_H 0xfff0707f #define MATCH_CRC32C_W 0x61a01013 #define MASK_CRC32C_W 0xfff0707f +#define MATCH_SH1ADD 0x20002033 +#define MASK_SH1ADD 0xfe00707f +#define MATCH_SH2ADD 0x20004033 +#define MASK_SH2ADD 0xfe00707f +#define MATCH_SH3ADD 0x20006033 +#define MASK_SH3ADD 0xfe00707f #define MATCH_CLMUL 0xa001033 #define MASK_CLMUL 0xfe00707f #define MATCH_CLMULR 0xa002033 @@ -628,6 +634,12 @@ #define MASK_CTZW 0xfff0707f #define MATCH_PCNTW 0x6020101b #define MASK_PCNTW 0xfff0707f +#define MATCH_SH1ADDU_W 0x2000203b +#define MASK_SH1ADDU_W 0xfe00707f +#define MATCH_SH2ADDU_W 0x2000403b +#define MASK_SH2ADDU_W 0xfe00707f +#define MATCH_SH3ADDU_W 0x2000603b +#define MASK_SH3ADDU_W 0xfe00707f #define MATCH_CLMULW 0xa00103b #define MASK_CLMULW 0xfe00707f #define MATCH_CLMULRW 0xa00203b @@ -2461,6 +2473,9 @@ DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) @@ -2513,6 +2528,9 @@ DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW) +DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W) +DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W) +DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W) DECLARE_INSN(clmulw, MATCH_CLMULW, MASK_CLMULW) DECLARE_INSN(clmulrw, MATCH_CLMULRW, MASK_CLMULRW) DECLARE_INSN(clmulhw, MATCH_CLMULHW, MASK_CLMULHW) |