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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-20 01:40:41 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-20 11:38:45 -0700 |
commit | f3ea0d7081f5156df776ac70e245d5d63a44f03a (patch) | |
tree | 0bb2521ee0b3a86426b5bcb805f5517b47b6c18e /riscv/decode.h | |
parent | 5720fb6d79c67d4a18de367aa546a1728202a407 (diff) | |
download | spike-f3ea0d7081f5156df776ac70e245d5d63a44f03a.zip spike-f3ea0d7081f5156df776ac70e245d5d63a44f03a.tar.gz spike-f3ea0d7081f5156df776ac70e245d5d63a44f03a.tar.bz2 |
rvv: refine ld_index
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index c9b33fe..fac0fe3 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1571,7 +1571,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ } \ P.VU.vstart = 0; -#define VI_LD_INDEX(stride, offset, ld_width, is_seg) \ +#define VI_LD_INDEX(elt_width, is_seg) \ VI_CHECK_LD_INDEX; \ const reg_t nf = insn.v_nf() + 1; \ const reg_t vl = P.VU.vl; \ @@ -1586,25 +1586,28 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ if (nf >= 2) \ require_noover(vd, nf, insn.rs2(), 1); \ const reg_t vlmul = P.VU.vlmul; \ + VI_DUPLICATE_VREG(insn.rs2(), elt_width); \ for (reg_t i = 0; i < vl; ++i) { \ VI_ELEMENT_SKIP(i); \ VI_STRIP(i); \ P.VU.vstart = i; \ for (reg_t fn = 0; fn < nf; ++fn) { \ - ld_width##_t val = MMU.load_##ld_width( \ - baseAddr + (stride) + (offset) * sizeof(ld_width##_t)); \ switch(P.VU.vsew){ \ case e8: \ - P.VU.elt<uint8_t>(vd + fn * vlmul, vreg_inx, true) = val; \ + P.VU.elt<uint8_t>(vd + fn * vlmul, vreg_inx, true) = \ + MMU.load_uint8(baseAddr + index[i] + fn * 1); \ break; \ case e16: \ - P.VU.elt<uint16_t>(vd + fn * vlmul, vreg_inx, true) = val; \ + P.VU.elt<uint16_t>(vd + fn * vlmul, vreg_inx, true) = \ + MMU.load_uint16(baseAddr + index[i] + fn * 2); \ break; \ case e32: \ - P.VU.elt<uint32_t>(vd + fn * vlmul, vreg_inx, true) = val; \ + P.VU.elt<uint32_t>(vd + fn * vlmul, vreg_inx, true) = \ + MMU.load_uint32(baseAddr + index[i] + fn * 4); \ break; \ default: \ - P.VU.elt<uint64_t>(vd + fn * vlmul, vreg_inx, true) = val; \ + P.VU.elt<uint64_t>(vd + fn * vlmul, vreg_inx, true) = \ + MMU.load_uint64(baseAddr + index[i] + fn * 8); \ break; \ } \ } \ |