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authorChih-Min Chao <chihmin.chao@sifive.com>2020-04-01 01:13:29 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-04-15 10:04:15 -0700
commitdb4962e2af32f784ea4aefeff743e167ac63d8f0 (patch)
tree6ec301511ee43a9f953c2f4ab086932505e45ca6 /riscv/decode.h
parent6ae23d6b144e07044d23cdb6bcd3dd4a2406ad89 (diff)
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rvv: add vmfxx f16 compare instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
-rw-r--r--riscv/decode.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index 1a20716..a86f712 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1865,10 +1865,18 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
DEBUG_RVV_FP_VF; \
VI_VFP_LOOP_END
-#define VI_VFP_LOOP_CMP(BODY32, BODY64, is_vs1) \
+#define VI_VFP_LOOP_CMP(BODY16, BODY32, BODY64, is_vs1) \
VI_CHECK_MSS(is_vs1); \
VI_VFP_LOOP_CMP_BASE \
switch(P.VU.vsew) { \
+ case e16: {\
+ float16_t vs2 = P.VU.elt<float16_t>(rs2_num, i); \
+ float16_t vs1 = P.VU.elt<float16_t>(rs1_num, i); \
+ float16_t rs1 = f16(READ_FREG(rs1_num)); \
+ BODY16; \
+ set_fp_exceptions; \
+ break; \
+ }\
case e32: {\
float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
float32_t vs1 = P.VU.elt<float32_t>(rs1_num, i); \
@@ -1885,7 +1893,6 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
set_fp_exceptions; \
break; \
}\
- case e16: \
default: \
require(0); \
break; \