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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 15:38:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:44:42 -0800 |
| commit | a11af65d0e30cd41fa25980686be701adcbb8ee0 (patch) | |
| tree | 019b1f9bab166f64e6bb04b4082839356906b0d6 /riscv/cfg.h | |
| parent | 8d084dbd092a916a2c26d9cb7f30d5651aa3181b (diff) | |
| download | spike-a11af65d0e30cd41fa25980686be701adcbb8ee0.zip spike-a11af65d0e30cd41fa25980686be701adcbb8ee0.tar.gz spike-a11af65d0e30cd41fa25980686be701adcbb8ee0.tar.bz2 | |
Add --[no-]misaligned command-line options
They don't do anything yet.
Diffstat (limited to 'riscv/cfg.h')
| -rw-r--r-- | riscv/cfg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/cfg.h b/riscv/cfg.h index 88d7fa1..1b09f65 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -52,6 +52,7 @@ public: const char *default_bootargs, const char *default_isa, const char *default_priv, const char *default_varch, + const bool default_misaligned, const endianness_t default_endianness, const reg_t default_pmpregions, const std::vector<mem_cfg_t> &default_mem_layout, @@ -62,6 +63,7 @@ public: isa(default_isa), priv(default_priv), varch(default_varch), + misaligned(default_misaligned), endianness(default_endianness), pmpregions(default_pmpregions), mem_layout(default_mem_layout), @@ -75,6 +77,7 @@ public: cfg_arg_t<const char *> isa; cfg_arg_t<const char *> priv; cfg_arg_t<const char *> varch; + bool misaligned; endianness_t endianness; reg_t pmpregions; cfg_arg_t<std::vector<mem_cfg_t>> mem_layout; |