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author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/cfg.h | |
parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/cfg.h')
-rw-r--r-- | riscv/cfg.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/riscv/cfg.h b/riscv/cfg.h index 6369bd8..dbdb58b 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -32,18 +32,22 @@ private: class mem_cfg_t { public: - mem_cfg_t(reg_t base, reg_t size) - : base(base), size(size) - { - // The truth of these assertions should be ensured by whatever is creating + static bool check_if_supported(reg_t base, reg_t size) { + // The truth of these conditions should be ensured by whatever is creating // the regions in the first place, but we have them here to make sure that // we can't end up describing memory regions that don't make sense. They // ask that the page size is a multiple of the minimum page size, that the // page is aligned to the minimum page size, that the page is non-empty and // that the top address is still representable in a reg_t. - assert((size % PGSIZE == 0) && + return (size % PGSIZE == 0) && (base % PGSIZE == 0) && - (base + size > base)); + (base + size > base); + } + + mem_cfg_t(reg_t base, reg_t size) + : base(base), size(size) + { + assert(mem_cfg_t::check_if_supported(base, size)); } reg_t base; @@ -57,6 +61,7 @@ public: const char *default_bootargs, const char *default_isa, const char *default_priv, const char *default_varch, + const reg_t default_pmpregions, const std::vector<mem_cfg_t> &default_mem_layout, const std::vector<int> default_hartids, bool default_real_time_clint) @@ -65,6 +70,7 @@ public: isa(default_isa), priv(default_priv), varch(default_varch), + pmpregions(default_pmpregions), mem_layout(default_mem_layout), hartids(default_hartids), explicit_hartids(false), @@ -76,6 +82,7 @@ public: cfg_arg_t<const char *> isa; cfg_arg_t<const char *> priv; cfg_arg_t<const char *> varch; + reg_t pmpregions; cfg_arg_t<std::vector<mem_cfg_t>> mem_layout; std::optional<reg_t> start_pc; cfg_arg_t<std::vector<int>> hartids; |