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author | Andrew Waterman <andrew@sifive.com> | 2020-05-10 00:13:38 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-19 19:57:06 -0700 |
commit | 65cfc4bca7db24a387fdc8c8f04d77c41617dc82 (patch) | |
tree | 80dc439d2b774a9feff267c473e9df4b46bd5ac4 /riscv/cachesim.h | |
parent | 1028871cf96008744744aa39d88c496a71792125 (diff) | |
download | spike-65cfc4bca7db24a387fdc8c8f04d77c41617dc82.zip spike-65cfc4bca7db24a387fdc8c8f04d77c41617dc82.tar.gz spike-65cfc4bca7db24a387fdc8c8f04d77c41617dc82.tar.bz2 |
Implement configurable PMP count
If no PMPs exist, simply deny access to the registers.
If some but not all PMPs exist, the others are hardwired to 0.
Diffstat (limited to 'riscv/cachesim.h')
0 files changed, 0 insertions, 0 deletions