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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-03-25 19:57:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-03-25 19:57:57 -0700 |
| commit | 614902fd205a1640ef9aeb7db3b75be3622d485b (patch) | |
| tree | 33313a203ebd09b74613be96278252160a0349ed /riscv/cachesim.h | |
| parent | 6d68f47aec9578a9a5d7f0476f49ded6df79932b (diff) | |
| download | spike-614902fd205a1640ef9aeb7db3b75be3622d485b.zip spike-614902fd205a1640ef9aeb7db3b75be3622d485b.tar.gz spike-614902fd205a1640ef9aeb7db3b75be3622d485b.tar.bz2 | |
support compilation with gcc 4.7
Diffstat (limited to 'riscv/cachesim.h')
| -rw-r--r-- | riscv/cachesim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/cachesim.h b/riscv/cachesim.h index d5dcf38..96631a0 100644 --- a/riscv/cachesim.h +++ b/riscv/cachesim.h @@ -22,7 +22,7 @@ class cache_sim_t public: cache_sim_t(size_t sets, size_t ways, size_t linesz, const char* name); cache_sim_t(const cache_sim_t& rhs); - ~cache_sim_t(); + virtual ~cache_sim_t(); void access(uint64_t addr, size_t bytes, bool store); void print_stats(); |