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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-21 16:09:31 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-03-03 13:47:54 -0600 |
| commit | e91d3a441e9391054eecd371922649b7f540cc52 (patch) | |
| tree | c52974e5461a3564f779ce13c615b3639ce2b060 | |
| parent | dfa7a56754c8362c9d183c4f0e16843124221669 (diff) | |
| download | spike-e91d3a441e9391054eecd371922649b7f540cc52.zip spike-e91d3a441e9391054eecd371922649b7f540cc52.tar.gz spike-e91d3a441e9391054eecd371922649b7f540cc52.tar.bz2 | |
Enforce 2-byte alignment of mepc/sepc/dpc
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 8cca490..943951b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -435,12 +435,12 @@ void processor_t::set_csr(int which, reg_t val) state.satp = val & (SATP64_PPN | SATP64_MODE); break; } - case CSR_SEPC: state.sepc = val; break; + case CSR_SEPC: state.sepc = val & ~(reg_t)1; break; case CSR_STVEC: state.stvec = val >> 2 << 2; break; case CSR_SSCRATCH: state.sscratch = val; break; case CSR_SCAUSE: state.scause = val; break; case CSR_STVAL: state.stval = val; break; - case CSR_MEPC: state.mepc = val; break; + case CSR_MEPC: state.mepc = val & ~(reg_t)1; break; case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break; case CSR_MSCRATCH: state.mscratch = val; break; case CSR_MCAUSE: state.mcause = val; break; @@ -510,7 +510,7 @@ void processor_t::set_csr(int which, reg_t val) state.dcsr.halt = get_field(val, DCSR_HALT); break; case CSR_DPC: - state.dpc = val; + state.dpc = val & ~(reg_t)1; break; case CSR_DSCRATCH: state.dscratch = val; |