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authorTim Newsome <tim@sifive.com>2018-03-09 17:54:07 -0800
committerAndrew Waterman <aswaterman@gmail.com>2018-03-09 19:54:07 -0600
commit64947480de005d94fb979260eff5751ca5b7d88d (patch)
tree0f94cc68da72603a611f3c4f10cb93fd2afd0829
parent9d1e10a36e771bf8cfbf515e07e856e021c1007a (diff)
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Fix single stepping csrrw instructions (#178)
This code is still a bit voodoo to me, but now we pass all the tests again. (Stepping was broken by 4299874ad4b07ef457776513a64e5b2397a6a75e.)
-rw-r--r--riscv/execute.cc15
1 files changed, 7 insertions, 8 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc
index f8f122a..b302daa 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -128,6 +128,13 @@ void processor_t::step(size_t n)
{
while (instret < n)
{
+ if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
+ state.single_step = state.STEP_NONE;
+ enter_debug_mode(DCSR_CAUSE_STEP);
+ // enter_debug_mode changed state.pc, so we can't just continue.
+ break;
+ }
+
if (unlikely(state.single_step == state.STEP_STEPPING)) {
state.single_step = state.STEP_STEPPED;
}
@@ -136,17 +143,9 @@ void processor_t::step(size_t n)
if (debug && !state.serialized)
disasm(fetch.insn);
pc = execute_insn(this, pc, fetch);
- bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
advance_pc();
- if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
- state.single_step = state.STEP_NONE;
- enter_debug_mode(DCSR_CAUSE_STEP);
- // enter_debug_mode changed state.pc, so we can't just continue.
- break;
- }
-
if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
state.pc < DEBUG_END)) {
// We're waiting for the debugger to tell us something.