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| author | Tim Newsome <tim@sifive.com> | 2018-07-17 13:38:26 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2019-03-04 09:19:10 -0800 |
| commit | 9a2904a97a1b157386555ec134e2f9b8f365ec36 (patch) | |
| tree | 3d0f1bb65d29b109f5466d318a1c76c77687e169 | |
| parent | f9d2be538b134ac42bf33b4b04e97d182ced5e36 (diff) | |
| download | spike-debug_rom.zip spike-debug_rom.tar.gz spike-debug_rom.tar.bz2 | |
Clean up/optimize Debug ROM.debug_rom
It's 3 instructions shorter now.
| -rwxr-xr-x | debug_rom/debug_rom.S | 13 | ||||
| -rw-r--r-- | debug_rom/debug_rom.h | 13 | ||||
| -rw-r--r-- | riscv/debug_rom_defines.h | 2 |
3 files changed, 11 insertions, 17 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 28c7076..f60b367 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -12,11 +12,10 @@ // their GO or RESUME bit is set. entry: - jal zero, _entry -resume: - jal zero, _resume + jal zero, _entry exception: - jal zero, _exception + sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. + // fall through to _entry _entry: // This fence is required because the execution may have written something @@ -40,10 +39,6 @@ entry_loop: bnez s0, resume jal zero, entry_loop -_exception: - sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. - ebreak - going: csrr s0, CSR_DSCRATCH // Restore s0 here sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. @@ -53,7 +48,7 @@ going: // so we use fence and fence.i for safety. (rocket-chip doesn't have this // because jalr is special there) -_resume: +resume: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. csrr s0, CSR_DSCRATCH // Restore s0 diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h index d21e166..57d65ca 100644 --- a/debug_rom/debug_rom.h +++ b/debug_rom/debug_rom.h @@ -1,12 +1,11 @@ static const unsigned char debug_rom_raw[] = { - 0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x40, 0x05, 0x6f, 0x00, 0x40, 0x03, - 0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1, - 0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00, - 0x63, 0x10, 0x04, 0x02, 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, - 0x13, 0x74, 0x24, 0x00, 0xe3, 0x18, 0x04, 0xfc, 0x6f, 0xf0, 0xdf, 0xfd, - 0x23, 0x26, 0x00, 0x10, 0x73, 0x00, 0x10, 0x00, 0x73, 0x24, 0x20, 0x7b, + 0x6f, 0x00, 0x80, 0x00, 0x23, 0x26, 0x00, 0x10, 0x0f, 0x00, 0xf0, 0x0f, + 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, + 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00, 0x63, 0x1c, 0x04, 0x00, + 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x24, 0x00, + 0x63, 0x1e, 0x04, 0x00, 0x6f, 0xf0, 0xdf, 0xfd, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x22, 0x00, 0x10, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00, 0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b }; -static const unsigned int debug_rom_raw_len = 104; +static const unsigned int debug_rom_raw_len = 92; diff --git a/riscv/debug_rom_defines.h b/riscv/debug_rom_defines.h index 616cf59..11e087a 100644 --- a/riscv/debug_rom_defines.h +++ b/riscv/debug_rom_defines.h @@ -18,6 +18,6 @@ // These needs to match the link.ld #define DEBUG_ROM_WHERETO 0x300 #define DEBUG_ROM_ENTRY 0x800 -#define DEBUG_ROM_TVEC 0x808 +#define DEBUG_ROM_TVEC 0x804 #endif |