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| author | Swapnil Ingle <swapnil.ingle@nutanix.com> | 2021-05-27 13:49:57 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-27 13:49:57 +0200 |
| commit | aaa19498e194368c80f2b12b7f380c911f98d9cc (patch) | |
| tree | 04616539ec3b172782ec26555ef21e1d4cfd5994 /test | |
| parent | e0690cf179293d983cb9a7837e7fa2ebc0308d30 (diff) | |
| download | libvfio-user-aaa19498e194368c80f2b12b7f380c911f98d9cc.zip libvfio-user-aaa19498e194368c80f2b12b7f380c911f98d9cc.tar.gz libvfio-user-aaa19498e194368c80f2b12b7f380c911f98d9cc.tar.bz2 | |
Fix struct pxcap (#534)
* Added missing reserved bits and renamed per to rer nameing as the
nvme specs
* Add pxcap capability in lspci test
Signed-off-by: Swapnil Ingle <swapnil.ingle@nutanix.com>
Reviewed-by: John Levon <john.levon@nutanix.com>
Diffstat (limited to 'test')
| -rw-r--r-- | test/lspci.expected.out.1 | 4 | ||||
| -rw-r--r-- | test/lspci.expected.out.2 | 4 | ||||
| -rw-r--r-- | test/lspci.expected.out.3 | 4 | ||||
| -rw-r--r-- | test/py/test_pci_caps.py | 2 |
4 files changed, 7 insertions, 7 deletions
diff --git a/test/lspci.expected.out.1 b/test/lspci.expected.out.1 index b01456a..300bc83 100644 --- a/test/lspci.expected.out.1 +++ b/test/lspci.expected.out.1 @@ -13,9 +13,9 @@ Capabilities: [48] Vendor Specific Information: Len=10 <?> Capabilities: [58] Express (v0) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us - ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- SlotPowerLimit 0.000W + ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset+ SlotPowerLimit 0.000W DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- - RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM not supported, Exit Latency L0s <64ns, L1 <1us diff --git a/test/lspci.expected.out.2 b/test/lspci.expected.out.2 index fc1abf6..0cde25c 100644 --- a/test/lspci.expected.out.2 +++ b/test/lspci.expected.out.2 @@ -13,9 +13,9 @@ Capabilities: [48] Vendor Specific Information: Len=10 <?> Capabilities: [58] Express (v0) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us - ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- SlotPowerLimit 0.000W + ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset+ SlotPowerLimit 0.000W DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- - RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM not supported diff --git a/test/lspci.expected.out.3 b/test/lspci.expected.out.3 index 4547644..d94cee3 100644 --- a/test/lspci.expected.out.3 +++ b/test/lspci.expected.out.3 @@ -13,9 +13,9 @@ Capabilities: [48] Vendor Specific Information: Len=10 <?> Capabilities: [58] Express (v0) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us - ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- SlotPowerLimit 0.000W + ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset+ SlotPowerLimit 0.000W DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- - RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM not supported diff --git a/test/py/test_pci_caps.py b/test/py/test_pci_caps.py index d510727..88a9b7c 100644 --- a/test/py/test_pci_caps.py +++ b/test/py/test_pci_caps.py @@ -309,7 +309,7 @@ def test_pci_cap_write_px(): #flrc cap = struct.pack("ccHHcc52c", to_byte(PCI_CAP_ID_EXP), b'\0', 0, 0, b'\0', - b'\x02', *[b'\0' for _ in range(52)]) + b'\x10', *[b'\0' for _ in range(52)]) pos = vfu_pci_add_capability(ctx, pos=cap_offsets[5], flags=0, data=cap) assert pos == cap_offsets[5] |