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| author | John Levon <john.levon@nutanix.com> | 2023-01-03 12:23:43 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-03 12:23:43 +0000 |
| commit | 3eb7ff6579740a5b962c1a52804b0ec5b29a4c42 (patch) | |
| tree | f7a519153645a4560eae19e3e9843adafef3cd9c /test/py/test_pci_caps.py | |
| parent | ad96efb02c27ec22116fb5800b48a6c9df27958f (diff) | |
| download | libvfio-user-3eb7ff6579740a5b962c1a52804b0ec5b29a4c42.zip libvfio-user-3eb7ff6579740a5b962c1a52804b0ec5b29a4c42.tar.gz libvfio-user-3eb7ff6579740a5b962c1a52804b0ec5b29a4c42.tar.bz2 | |
fix FLR reset callback (#729)
A reset callback is allowed to call functions disallowed in quiescent
state. However, the FLR reset path neglected to account for this
properly, causing an incorrect assert to be triggered if, for example,
vfu_sgl_put() is called. To fix this, make sure all reset paths go
through call_reset_cb().
Signed-off-by: John Levon <john.levon@nutanix.com>
Reviewed-by: Thanos Makatos <thanos.makatos@nutanix.com>
Diffstat (limited to 'test/py/test_pci_caps.py')
| -rw-r--r-- | test/py/test_pci_caps.py | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/test/py/test_pci_caps.py b/test/py/test_pci_caps.py index 24e992f..edd1683 100644 --- a/test/py/test_pci_caps.py +++ b/test/py/test_pci_caps.py @@ -314,16 +314,6 @@ def __test_pci_cap_write_pmcs(sock): count=len(data), data=data, expect=errno.ENOTSUP) -def _setup_flrc(ctx): - # flrc - cap = struct.pack("ccHHcc52c", to_byte(PCI_CAP_ID_EXP), b'\0', 0, 0, b'\0', - b'\x10', *[b'\0' for _ in range(52)]) - # FIXME adding capability after we've realized the device only works - # because of bug #618. - pos = vfu_pci_add_capability(ctx, pos=0, flags=0, data=cap) - assert pos == PCI_STD_HEADER_SIZEOF - - @patch("libvfio_user.reset_cb", return_value=0) @patch('libvfio_user.quiesce_cb') def test_pci_cap_write_px(mock_quiesce, mock_reset): @@ -333,7 +323,7 @@ def test_pci_cap_write_px(mock_quiesce, mock_reset): setup_pci_dev(realize=True) sock = connect_client(ctx) - _setup_flrc(ctx) + setup_flrc(ctx) # iflr offset = PCI_STD_HEADER_SIZEOF + 8 @@ -421,7 +411,7 @@ def test_pci_cap_write_pxdc2(): setup_pci_dev(realize=True) sock = connect_client(ctx) - _setup_flrc(ctx) + setup_flrc(ctx) offset = (vfu_pci_find_capability(ctx, False, PCI_CAP_ID_EXP) + PCI_EXP_DEVCTL2) @@ -436,9 +426,10 @@ def test_pci_cap_write_pxdc2(): def test_pci_cap_write_pxlc2(): setup_pci_dev(realize=True) - _setup_flrc(ctx) - sock = connect_client(ctx) + + setup_flrc(ctx) + offset = (vfu_pci_find_capability(ctx, False, PCI_CAP_ID_EXP) + PCI_EXP_LNKCTL2) data = b'\xbe\xef' |