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2018-07-21rockchip: i2c: enable i2c controller for rk3066 and rk3188Alexander Kochetkov1-5/+89
rk3066 and rk3188 has two I2C controller implementations. Current I2C driver wan't work with legacy implementation. Switching between controllers is performed using a bit inside GFR_SOC_CON1 register. The bit setting is performed by pinctrl driver. The patch ask pinctrl to do settings. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fix warnings by including the rk3228 variant in the compatible-list]: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-20stm32mp1: clk: support digital bypassPatrick Delaunay1-9/+18
HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: add ADC clock gatingPatrick Delaunay1-0/+7
Add ADC clock gating, that may be used by STM32 ADC. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: update Ethernet clock gatingPatrick Delaunay1-2/+1
Alignment with kernel clock driver Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: add LDTC and DSI clock supportPatrick Delaunay1-3/+93
This patch add clk_enable/clk_disable/clk_get_rate support for - DSI_PX - LTDC_PX - DSI_K (only get rate) These clocks are needed for LTDC and DSI drivers with latest device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20stm32mp1: clk: add common function pll_get_fvcoPatrick Delaunay1-30/+61
the function compute the VCO PLL freq, used in - stm32mp1_read_pll_freq() - pll_set_rate() Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> # Conflicts: # drivers/clk/clk_stm32mp1.c
2018-07-20stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macroPatrick Delaunay1-9/+6
This patch define RCC_PLLNCFGR2_SHIFT to reuse it in the pll function for set rate. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-07-20misc: stm32: Add STM32MP1 supportPatrick Delaunay4-24/+19
Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20sysreset: syscon: update regmap access to sysconPatrick Delaunay1-7/+9
Use new API syscon_node_to_regmap in sysreset_syscon driver for compatible "syscon-reboot"; that's avoid the need of explicit syscon binding for "regmap" handle. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20drivers: rtc: correct week day for mc146818Heinrich Schuchardt1-2/+6
For qemu-x86 the date command produces wrong days of the week: Date: 2018-07-06 (Saturday) Time: 18:02:03 Date: 2018-07-07 (unknown day) Time: 21:02:06 According to a comment in the Linux driver the mc146818 only updates the day of the week if the register value is non-zero. Sunday is 1, saturday is 7 unlike in U-Boot (see data sheet https://www.nxp.com/docs/en/data-sheet/MC146818.pdf). So let's use our library function to determine the day of the week. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-07-19drivers: rtc: resolve year 2038 problem in rtc_to_tmHeinrich Schuchardt4-44/+77
Our implementation of rtc_to_tm() cannot handle dates of more than 0x7fffffff seconds after 1970-01-01. Adopt the Linux kernel implementation. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-07-19drivers: smem: sandboxRamon Fried3-0/+55
Add Sandbox driver for SMEM. mostly stub operations. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19soc: qualcomm: Add Shared Memory Manager driverRamon Fried4-0/+948
The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Adapted from the Linux driver (4.17) Changes from the original Linux driver: * Removed HW spinlock mechanism, which is irrelevant in U-boot particualar use case, which is just reading from the smem. * Adapted from Linux driver model to U-Boot's. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19dm: SMEM (Shared memory) uclassRamon Fried4-0/+53
This is a uclass for Shared memory manager drivers. A Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-19ARM: qemu-arm: enable RTCHeinrich Schuchardt1-0/+7
QEMU provides an emulated ARM AMBA PrimeCell PL031 RTC. The patch sets the base address in the board include file according to the definition in hw/arm/virt.c of the QEMU source. It defines the Kconfig option for the existing driver, and enables the RTC driver in qemu_arm64_defconfig and qemu_arm_defconfig as well as the date command. We need an RTC to provide the GetTime() runtime service in the UEFI subsystem. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Tested-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2018-07-19power: regulator: stpmu1: add power off delayChristophe Kerello1-8/+12
This patch adds a delay when regulators are disabled. This delay is set to 5 ms to cover all use cases. The worst use case actually seen is during a SD card power cycle. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-19phy: Be able to get phy from PHY providerPatrice Chotard1-2/+15
In case of phy are provided from a PHY provider nodes as following: usbphyc: usb-phy@5a006000 { compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc_clk USBPHY_K>; resets = <&rcc_rst USBPHY_R>; #address-cells = <1>; #size-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <0>; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; vdda1v1-supply = <&reg11>; vdda1v8-supply = <&reg18> #phy-cells = <1>; }; }; and PHY are called as following: usbh_ehci: usbh-ehci@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc_clk USBH>; resets = <&rcc_rst USBH_R>; interrupts = <GIC_SPI 75 IRQ_TYPE_NONE>; companion = <&usbh_ohci>; phys = <&usbphyc_port0>; phy-names = "usb"; status = "okay"; }; generic_phy_get_by_index() must be updated to first look for PHY phandle as previously and in case of error looks for PHY provider by finding the parent's current node which is the PHY provider. args (ofnode_phandle_args struct) must also be updated by inserting the phy index into the PHY provider as args[0]. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-19mmc: stm32_sdmmc2: update pwron managementPatrick Delaunay1-11/+67
Correctly manage the SDMMC reset and card cycle power to fully handle the power cycle added in the MMC uclass and avoid issue with level-shifter with some uSDCARD. 3 states managed in driver: 1/ reset: SDMMC disable, signal HiZ 2/ power-cycle: SDMMC disable, signals drive to 0 3/ power-on: SDMMC enabled Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-19drivers: fpga: zynqpl: fix compilation with SPLLuis Araneda1-2/+2
Disable the use of function zynq_loadfs when compiling the driver for the SPL, as the following filesystem functions are not found by the linker: - fs_set_blk_dev - fs_read - fs_set_blk_dev - fs_read - fs_read Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: cadence: Do not stop wdt in probeMichal Simek1-2/+0
Watchdog can be started before probe and u-boot should just take control over it. That's why do not stop watchdog in probe to cover cases where watchdog can expire before probe and start. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: cdns: Add comment for expire_now functionMichal Simek1-0/+1
IP itself has no reg/no bit which can be used for this functionality. Add this note to the driver to make sure that none will be asking for that. Current method is to setup 1s timeout and hang() which is done via wdt_expire_now(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19microblaze: Convert generic platform to DM gpioMichal Simek1-0/+1
Converting GPIO to DM requires to do changes in reset subsystem that's why support for Microblaze soft reset via sysreset and GPIO sysreset support was added. These two patches enables enabling GPIO DM. Microblaze soft reset is bind at last reset method. GPIO reset is handled via sysreset with adding this fragment to DT. gpio-restart { compatible = "gpio-restart"; gpios = <&reset_gpio 0 0 0>; /* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */ }; hard-reset-gpio property is not documented and also handled. Conversion is required. Unfortunately do_reset is required for SPL that's why use only soft microblaze reset for now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: Convert Xilinx Axi watchdog driver to driver modelShreenidhi Shedi2-26/+93
Xilinx Axi wdt driver conversion to driver model & Kconfig update for the same. Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19gpio: xilinx: Convert driver to DMMichal Simek1-1/+264
This patch is enabling GPIO_DM support to have an option to use this driver together with zynq gpio driver. !DM part is kept there till Microblaze is cleanup which will be done hopefully soon. Just a note: There is no reason to initialize uc-priv->name because it is completely unused. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19sysreset: Add support for Microblaze soft reset jumpMichal Simek3-0/+37
Microblaze is storing reset vector at address 0x0. It means soft reset can be done by just jumping to this address. This code was in platform code but sysreset interface is providing enough capabilities to have more options how to reset the system. It can go from gpio reset through watchdog reset till soft reset. The driver has not compatible string because this is cpu specific and DM core is not able to detect compatible string in DT root that's why this driver will be instantiated from platform code by calling device_bind_driver(gd->dm_root, "mb_soft_reset", "reset_soft", NULL); It should be bind as the last reset method to ensure that hw reset is called before this. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19sysreset: Add support for gpio-restartMichal Simek3-0/+68
The Linux kernel has binding for gpio-restart node. This patch is adding basic support without supporting any optional properties. This driver was tested on Microblaze system where gpio is connected to SoC reset logic. Output value is handled via gpios cells values. In gpio_reboot_request() set_value is writing 1 because dm_gpio_set_value() is capable to changing it when it is ACTIVE_LOW. ... if (desc->flags & GPIOD_ACTIVE_LOW) value = !value; ... Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: zynq: Setup bank_name to dev->nameMichal Simek1-0/+2
There should be proper bank name setup to distinguish between different gpio drivers. Use dev->name for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: zynq: Read of mach data in platdata with dev_get_driver_dataMichal Simek1-27/+2
Remove bogus zynq_gpio_getplat_data() and read driver data directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: dm: Support manual relocation for gpioMichal Simek1-0/+35
Relocate gpio ops as was done by: "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19sysreset: dm: Support manual relocation for sysresetMichal Simek1-0/+16
Relocate sysreset ops as was done by: "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19gpio: zynq: Fix typo in one error messageMichal Simek1-1/+1
Just fix error message. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19watchdog: dm: Support manual relocation for watchdogsMichal Simek1-0/+23
Relocate watchdog ops as was done by: "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19watchdog: dm: Change uclass name to watchdog and enable DM_UC_FLAG_SEQ_ALIASMichal Simek1-1/+2
uclass name is used by dev_read_alias_seq which return seq number when aliases are used. Code fragment: 168 int dev_read_alias_seq(struct udevice *dev, int *devnump) 169 { 170 ofnode node = dev_ofnode(dev); 171 const char *uc_name = dev->uclass->uc_drv->name; 172 int ret; 173 174 if (ofnode_is_np(node)) { 175 ret = of_alias_get_id(ofnode_to_np(node), uc_name); Also this patch enables DM_UC_FLAG_SEQ_ALIAS to be in sync with Linux which is also using watchdog name for watchdog aliases. drivers/watchdog/watchdog_core.c:215: ret = of_alias_get_id(wdd->parent->of_node, "watchdog"); Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19xilinx: zynq: Add support to secure imagesSiva Durga Prasad Paladugu1-0/+45
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19serial: zynq: Use platdata for storing static data instead of privMichal Simek1-16/+16
Explanation from Simon Glass "Private data is created when the device is probed and freed when the device is removed. Platform data is created when the device is bound, and survives probe/remove cycles. Strictly speaking, platform data should be used to hold the decoded device tree properties. Private data should be used for run-time things the device needs to keep track of." Based on description the driver needs to be switch to use platdata instead of priv. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-19clk: zynqmp: Fixed the same if/else part error reported by coverityVipul Kumar1-2/+4
This patch fixed the same if/else part error by adding the required source select on the basis of is_pre_src check. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19gpio: zynq: Use live-tree functionMichal Simek1-1/+1
Use live-tree function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-17Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2-42/+75
2018-07-16sf: add paired dev info for winbond w25q16jvLudwig Zenz1-1/+1
This commit adds paired dev info for winbond w25q16jv (tested w25q16jvssiq with a i.mx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16sf: add Macronix mx25l1633e entryLudwig Zenz1-0/+1
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16sf: add Gigadevice gd25q16c entryLudwig Zenz1-0/+1
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi_flash: add a bunch of winbond flashes to id-tableHannes Schmelzer1-0/+5
This commit adds the following flashes to the id-table - W25Q16JV - W25Q32JV - W25Q64JV - W25Q128JV - W25Q256JV Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: zynqmp_gqspi: Add support for ZynqMP qspi driverSiva Durga Prasad Paladugu3-0/+737
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> [jagan: removed GQSPI_MIO_NUM_ macros] Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: convert to livetreeVipul Kumar1-3/+2
Update the xilinx spi driver to support a live tree. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Added support to read JEDEC-id twice at the boot timeVipul Kumar1-0/+41
This patch is for the startup block issue in the spi controller. SPI clock is passing through STARTUP block to FLASH. STARTUP block don't provide clock as soon as QSPI provides command. So, first command fails. This patch added support to read JEDEC id in xilinx_spi_xfer (). Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() functionVipul Kumar1-35/+68
This patch modify xilinx_spi_xfer() function and add rxfifo() and txfifo() functions to add the modularity so that these functions can be used by other functions within the same file. This patch also added support to read fifo_size from dts. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx: Read reg base address from DTS fileMichal Simek1-6/+1
This patch added support to read register base address from DTS file. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: support R40 GMACLothar Felten1-26/+53
Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: set mux and clock by driver dataLothar Felten1-15/+20
Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16net: sun8i-emac: fix printing NULL characterLothar Felten1-2/+1
If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
generated by cgit v1.1 at 2024-10-09 23:53:54 +0000