rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-07-06	drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'	Green Wan	1	-3/+3
2021-05-31	drivers: clk: add fu740 support	Green Wan	8	-753/+1286
2021-01-05	dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()	Simon Glass	1	-1/+1
2020-12-13	dm: treewide: Rename auto_alloc_size members to be shorter	Simon Glass	1	-1/+1
2020-10-15	clk: sifive: Include device_compat.h	Sean Anderson	1	-7/+7
2020-08-04	sifive: reset: add DM based reset driver for SiFive SoC's	Sagar Shrikant Kadam	1	-15/+58
2020-08-04	fu540: prci: use common reset indexes defined in binding header	Sagar Shrikant Kadam	1	-10/+7
2020-06-04	clk: sifive: fu540-prci: Release ethernet clock reset	Pragnesh Patel	1	-0/+20
2020-06-04	clk: sifive: fu540-prci: Add ddr clock initialization	Pragnesh Patel	1	-6/+45
2020-06-04	clk: sifive: fu540-prci: Add clock enable and disable ops	Pragnesh Patel	1	-12/+96
2020-05-18	common: Drop linux/delay.h from common header	Simon Glass	1	-0/+1
2020-02-05	dm: core: Require users of devres to include the header	Simon Glass	1	-0/+1
2019-07-19	clk: sifive: Drop GEMGXL clock driver	Anup Patel	3	-69/+0
2019-07-19	clk: sifive: Sync-up main driver with upstream Linux	Anup Patel	1	-36/+60
2019-07-19	clk: sifive: Sync-up DT bindings header with upstream Linux	Anup Patel	1	-1/+1
2019-07-19	clk: sifive: Sync-up WRPLL library with upstream Linux	Anup Patel	1	-13/+13
2019-07-19	clk: sifive: Factor-out PLL library as separate module	Anup Patel	5	-498/+1
2019-06-01	clk: sifive: Add clock driver for GEMGXL MGMT	Bin Meng	3	-0/+69
2019-05-09	clk: sifive: fu540-prci: Change include order	Jagan Teki	1	-1/+1
2019-02-27	clk: Add SiFive FU540 PRCI clock driver	Anup Patel	5	-0/+1119