rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2009-07-22	85xx, 86xx: Add common board_add_ram_info()	Peter Tyser	2	-41/+98
2009-07-01	fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more	Timur Tabi	1	-1/+1
2009-06-12	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	Kumar Gala	7	-39/+41
2009-03-30	fsl-ddr: add the DDR3 SPD infrastructure	Dave Liu	5	-46/+754
2009-03-30	fsl-ddr: Fix two bugs in the ddr infrastructure	Dave Liu	1	-1/+4
2009-02-16	fsl-ddr: Allow system to boot if we have more than 4G of memory	Kumar Gala	1	-1/+1
2009-02-16	fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller	Kumar Gala	1	-0/+4
2009-01-23	fsl-ddr: use the 1T timing as default configuration	Dave Liu	1	-1/+1
2009-01-23	fsl-ddr: make the self refresh idle threshold configurable	Dave Liu	1	-4/+8
2009-01-23	fsl-ddr: clean up the ddr code for DDR3 controller	Dave Liu	1	-11/+13
2009-01-23	fsl-ddr: update the bit mask for DDR3 controller	Dave Liu	1	-4/+8
2008-12-03	fsl ddr skip interleaving if not supported.	Ed Swarthout	2	-12/+17
2008-10-18	Add debug information for DDR controller registers	Haiying Wang	1	-0/+13
2008-10-18	Check DDR interleaving mode	Haiying Wang	2	-5/+112
2008-10-18	Pass dimm parameters to populate populate controller options	Haiying Wang	4	-87/+7
2008-10-18	Make DDR interleaving mode work correctly	Haiying Wang	2	-12/+54
2008-10-18	rename CFG_ macros to CONFIG_SYS	Jean-Christophe PLAGNIOL-VILLARD	1	-7/+7
2008-09-13	Coding style cleanup, update CHANGELOG	Wolfgang Denk	1	-15/+15
2008-09-07	Fix compiler warning in mpc8xxx ddr code	Kumar Gala	1	-2/+4
2008-08-27	FSL DDR: Add DDR2 DIMM paramter support	Kumar Gala	1	-0/+339
2008-08-27	FSL DDR: Add DDR1 DIMM paramter support	Kumar Gala	1	-0/+343
2008-08-27	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	Kumar Gala	9	-0/+2418