rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2024-05-20	Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-next	Tom Rini	1	-1/+0
	As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19	Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""	Tom Rini	1	-0/+1
	When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07	board: openpiton: Remove <common.h> and add needed includes	Tom Rini	1	-1/+0
	Remove <common.h> from this board vendor directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-12	riscv: Rename SiFive CLINT to RISC-V ALINT	Bin Meng	1	-1/+1
	As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-31	Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE	Simon Glass	1	-1/+1
	The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-07	riscv: dts: add OpenPiton RISC-V board dts support	Tianrui Wei	1	-1/+2
	Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06	board: riscv: add openpiton-riscv64 SoC support	Tianrui Wei	4	-0/+86
	This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>