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2021-06-11common: fit: Update board_fit_image_post_process() to pass fit and node_offsetLokesh Vutla3-3/+6
board_fit_image_post_process() passes only start and size of the image, but type of the image is not passed. So pass fit and node_offset, to derive information about image to be processed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11arm: mach-k3: introduce new config option for sysfw splitTero Kristo1-0/+11
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run under two cores, TIFS portion on DMSC core, and DM firmware under MCU R5. As MCU R5 is also used to run one phase of the bootloader, we must prevent access from here towards sysfw services. To support this, add new config option which can be used to detect presence of RM/PM sysfw services. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-09arm: dts: sync rtc node of am335x boards with Linux 5.9-rc7Dario Binacchi4-0/+21
There have been some changes to the am335x-<board> DTs related to the rtc node, so let's re-syncs them with Linux. Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210602203805.11494-7-dariobin@libero.it
2021-06-09arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its ↵Aswath Govindraju1-1/+1
max size Due to a limitation for USB DFU boot mode, SPL load address has to be less than or equal to 0x70001000. So, load address of SPL and ATF have been moved to 0x70000000 and 0x701a0000 respectively. Also, the maximum size of ATF has been increased to 0x1c000 [1]. Therefore, update ATF's location and maximum size accordingly in the device tree file. [1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9 Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-10-a-govindraju@ti.com
2021-06-09configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy ↵Aswath Govindraju1-4/+2
the limitations for USB DFU boot mode For USB DFU boot mode there is a limitation on the load address of boot images that they have to be less than 0x70001000. Therefore, move the SPL_TEXT_BASE address to 0x70000000. Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at 0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move the location of ATF to a latter location in SRAM, past the SPL image. Also rearrange the EEPROM and BSS data on top of ATF. Given below is the placement of various data sections in SRAM ┌──────────────────────────────────────┐0x70000000 │ │ │ │ │ │ │ SPL IMAGE (Max size 1.5 MB) │ │ │ │ │ │ │ ├──────────────────────────────────────┤0x7017FFFF │ │ │ SPL STACK │ │ │ ├──────────────────────────────────────┤0x70192727 │ GLOBAL DATA(216 B) │ ├──────────────────────────────────────┤0x701927FF │ │ │ INITIAL HEAP (32 KB) │ │ │ ├──────────────────────────────────────┤0x7019A7FF │ │ │ BSS (20 KB) │ ├──────────────────────────────────────┤0x7019F7FF │ EEPROM DATA (2 KB) │ ├──────────────────────────────────────┤0x7019FFFF │ │ │ │ │ ATF (123 KB) │ │ │ │ │ ├──────────────────────────────────────┤0x701BEBFB │ BOOT PARAMETER INDEX TABLE (5124 B)│ ├──────────────────────────────────────┤0x701BFFFF │ │ │SYSFW FIREWALLED DUE TO A BUG (128 KB)│ │ │ ├──────────────────────────────────────┤0x701DFFFF │ │ │ DMSC CODE AREA (128 KB) │ │ │ └──────────────────────────────────────┘0x701FFFFF Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-9-a-govindraju@ti.com
2021-06-09arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to ↵Aswath Govindraju1-0/+13
peripheral for USB subsystem Add U-Boot tags and fix the dr_mode as peripheral in U-Boot to support DFU by default. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-8-a-govindraju@ti.com
2021-06-09arm: dts: k3-am642-*-evm: Add USB supportAswath Govindraju2-0/+36
AM64 EVM board has a micro USB 2.0 AB connector and the USB0_VBUS is connected with a resistor divider in between. USB0_DRVVBUS pin is muxed between USB0_DRVVBUS and GPIO1_79 signals. Add the corresponding properties and set the pinmux mode for USB subsystem in the evm dts file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-7-a-govindraju@ti.com
2021-06-09arm: dts: k3-am64-main: Add USB DT nodesAswath Govindraju1-0/+30
Add DT node for the single USB subsystem in main dtsi file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-6-a-govindraju@ti.com
2021-06-09arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modesAswath Govindraju1-0/+33
U-Boot either supports USB host or device mode for a node at a time in the device tree nodes. To support both host and dfu bootmodes, dr_mode is set to "peripheral" by default and then fixed based on the mode selected by the boot mode config dip switches on the board. This needs to happen before the cdns3 generic layer binds the usb device to a host or a device driver. Therefore, use fdtdec_setup_board() implementation to fixup the device tree property. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-4-a-govindraju@ti.com
2021-06-09arm: mach-k3: am642_init: Add support for USB boot modeAswath Govindraju3-4/+20
Add support for identifying USB host and device boot modes Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-3-a-govindraju@ti.com
2021-06-09tools: k3_fit_atf: Add support for providing ATF load address using a ↵Aswath Govindraju2-0/+8
Kconfig symbol Add support for providing ATF load address with a Kconfig symbol. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210604163043.12811-2-a-govindraju@ti.com
2021-06-09arm: dts: k3-j7200: ddr: Update to 0.5.0 version of DDR for LPDDR 2666MTsKevin Scholz2-219/+220
Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 2666MTs LPDDR configuration on J7200. Signed-off-by: Kevin Scholz <k-scholz@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210603131453.11414-1-praneeth@ti.com
2021-06-07stm32mp: don't map the reserved region with no-map propertyWIP/2021-06-07-arm-cache-cp15-improvementsPatrick Delaunay1-2/+15
No more map the reserved region with "no-map" property by marking the corresponding TLB entries with invalid entry (=0) to avoid speculative access. The device tree parsing done in lmb_init_and_reserve() takes a long time when it is executed without data cache, so it is called in enable_caches() before to disable it. This patch fixes an issue where predictive read access on secure DDR OP-TEE reserved area are caught by firewall. Series-cc: marex Series-cc: pch Series-cc: marek.bykowski@gmail.com Series-cc: Ard Biesheuvel <ardb@kernel.org> Series-cc: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-07stm32mp: Increase the reserved memory in board_get_usable_ram_topPatrick Delaunay1-2/+5
Add 8M for the U-Boot reserved memory (display, fdt, gd, ...) mapped cacheable before relocation. Without this patch the device tree, located before the MALLOC area is not tagged cacheable just after relocation, before mmu reconfiguration. This patch reduces the duration for device tree parsing in lmb_init_and_reserve. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-05sandbox: correct determination of the text baseHeinrich Schuchardt1-1/+4
os_find_text_base() assumes that first line of /proc/self/maps holds information about the text. Hence we must call the function before calling os_malloc() which calls mmap(0x10000000,). Failure to do so has led to incorrect values for pc_reloc when an exception was reported => exception undefined Illegal instruction pc = 0x5628d82e9d3c, pc_reloc = 0x5628c82e9d3c as well as incorrect output of the bdinfo command => bdinfo relocaddr = 0x0000000007858000 reloc off = 0x0000000010000000 Fixes: b308d9fd18fa ("sandbox: Avoid using malloc() for system state") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-04arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiBPali Rohár1-3/+10
For some configurations with more PCIe cards and PCIe bridges, 16 MiB of PCIe MEM space may not be enough. Since TF-A already allocates a 128 MiB CPU window for PCIe, and since IO port space is only 64 KiB in total, use all the remaining space (64 + 32 + 16 + 8 + 4 + 2 + 1 = 127 MiB) for PCIe MEM. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-04arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() functionPali Rohár1-14/+60
Current version of this function uses a lot of incorrect assumptions about the `ranges` DT property: * parent(#address-cells) == 2 * #size-cells == 2 * number of entries == 2 * address size of first entry == 0x1000000 * second child address entry == base + 0x1000000 Trying to increase PCIe MEM space to more than 16 MiB leads to an overlap with PCIe IO space, and trying to define additional MEM space (as a third entry in the `ranges` DT property) causes U-Boot to crash when booting the kernel. ## Flattened Device Tree blob at 04f00000 Booting using the fdt blob at 0x4f00000 Loading Device Tree to 000000001fb01000, end 000000001fb08f12 ... OK ERROR: board-specific fdt fixup failed: <unknown error> - must RESET the board to recover. Fix a3700_fdt_fix_pcie_regions() to properly parse and update all addresses in the `ranges` property according to https://elinux.org/Device_Tree_Usage#PCI_Address_Translation Now it is possible to increase PCIe MEM space from 16 MiB to maximal value of 127 MiB. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Fixes: cb2ddb291ee6 ("arm64: mvebu: a37xx: add device-tree fixer for PCIe regions") Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-04arm: a37xx: pci: Find PCIe controller node by compatible instead of pathPali Rohár1-3/+1
Find PCIe DT node by compatible string instead of retrieving it by using hardcoded DT path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-04arm: a37xx: pci: Fix DT compatible string to Linux' DT compatiblePali Rohár1-1/+1
Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie' to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible with Linux' DT node. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-05-31Merge https://source.denx.de/u-boot/custodians/u-boot-riscvWIP/31May2021Tom Rini19-1/+2525
- SiFive FU740 and Unmatched support
2021-05-31riscv: cpu: fu740: clear feature disable CSRGreen Wan1-0/+15
Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31board: sifive: add HiFive Unmatched board supportGreen Wan1-0/+4
Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31riscv: dts: add SiFive Unmatched board supportGreen Wan4-0/+1790
Add dts files for SiFive Unmatched board. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31riscv: dts: add fu740 supportGreen Wan2-0/+434
Add dts support for fu740. The HiFive Unmatched support is based on fu740 cpu and drivers in following patch set. Signed-off-by: Green Wan <green.wan@sifive.com> [greentime.hu: set fu740 speed to 1.2GHz] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31drivers: clk: add fu740 supportGreen Wan1-1/+1
Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by: Green Wan <green.wan@sifive.com>
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan12-0/+281
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-31sunxi: Bring back SD card as MMC device 0Andre Przywara1-0/+1
Commit 2243d19e5618 ("mmc: mmc-uclass: Use dev_seq() to read aliases node's index") now actually enforces U-Boot's device enumeration policy, where explicitly named devices come first, then any other non-named devices follow, without filling gaps. For quite a while we have had an "mmc1 = &mmc2;" alias in our sunxi-u-boot.dtsi, which now leads to the problem that the SD card (which was always mmc device 0) now gets to be number 2. This breaks quite some boot scripts, including our own distro boot commands, and some other features looking at $mmc_bootdev, also fastboot. Just add an explicit mmc0 alias in the very same file to fix this and restore the old behaviour. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Samuel Holland <samuel@sholland.org> Tested-by: Simon Baatz <gmbnomis@gmail.com>
2021-05-28arm: dts: stm32mp157c-odyssey-som: enable the RNG1Grzegorz Szymaszek1-0/+4
Enable the true random number generator. It can be used, for example, to generate partition UUIDs when partitioning with the gpt command. The generator is already enabled in the device trees of several other STM32MP1‐based boards, like DKx or DHCOM. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-05-27Merge tag 'ti-v2021.07-rc4' of ↵WIP/27May2021Tom Rini3-0/+16
https://source.denx.de/u-boot/custodians/u-boot-ti - Fix reset for AM64 platforms - Enable networking PHY driver for AM64 - Fix default R5F cluster setting in J7
2021-05-27arm: dts: k3-am642-sk: Add sysreset controller nodeSuman Anna1-0/+4
The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 SK. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-27arm: dts: k3-am642-evm: Add sysreset controller nodeSuman Anna1-0/+4
The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 EVM. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-27arm: dts: k3-j721e: Fix up MAIN R5FSS cluster mode back to Split-modeSuman Anna1-0/+8
The default U-Boot environment variables and design are all set up for both the MAIN R5FSS clusters to be in Split-mode. This is the setting in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3ef8f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The modes for both the clusters got switched back to LockStep mode by mistake in commit 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot") also in v2021.04-rc2. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f at 5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data at addr=0x82000000 98484 bytes: Failed! k3_r5f_rproc r5f at 5f00000: Invalid op: Trying to start secondary core 9 in lockstep mode Load Remote Processor 5 with data at addr=0x82000000 98484 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot") Reported-by: Minas Hambardzumyan <minas@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-26powerpc: fix regression in arch_initr_trap()Matt Merhar1-0/+1
The assembly output of the arch_initr_trap() function differed by a single byte after common.h was removed from traps.c: fff49a18 <arch_initr_trap>: fff49a18: 94 21 ff f0 stwu r1,-16(r1) fff49a1c: 7c 08 02 a6 mflr r0 fff49a20: 90 01 00 14 stw r0,20(r1) -fff49a24: 80 62 00 44 lwz r3,68(r2) +fff49a24: 80 62 00 38 lwz r3,56(r2) fff49a28: 4b ff 76 19 bl fff41040 <trap_init> fff49a2c: 80 01 00 14 lwz r0,20(r1) fff49a30: 38 60 00 00 li r3,0 fff49a34: 38 21 00 10 addi r1,r1,16 fff49a38: 7c 08 03 a6 mtlr r0 This was causing a consistent hard lockup during the MMC read / loading of the QoriQ FMan firmware on a P2041RDB board. Re-adding the header causes identical assembly to be emitted and allows the firmware loading and subsequent boot to succeed. Fixes: 401d1c4f5d ("common: Drop asm/global_data.h from common header") Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
2021-05-25MIPS: remove deprecated qemu_mips boardDaniel Schwierzeck1-11/+0
Remove qemu_mips boards because DM migration doesn't make sense. The board support for qemu_mips is already marked as deprecated in Qemu in favour of the Malta board. Also qemu_mips support has been removed from Linux a long time ago. The official replacement is the Malta board. The same Malta U-Boot image can be used with Qemu and on physical hardware. All combinations of Big Endian and Little Endian as well as 32 bit and 64 bit are supported. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-05-24ARM: don't use --gc-sections with LTO when using private libgccMarek Behún1-0/+2
When using LTO, we can throw away the --gc-sections flag, but only if using private libgcc. When using system's libgcc, --gc-sections is still needed, otherwise linking will fail due to undefined references to libc's symbols. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24ARM: don't use -ffunction-sections/-fdata-sections with LTO buildMarek Behún1-2/+6
When building with LTO, using -ffunction-sections/-fdata-sections is not useful anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24ARM: make LTO availableMarek Behún2-0/+3
Make LTO available for ARM architecture. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24armv8: SPL: discard relocation informationMarek Behún1-0/+1
For some reason when building SPL for ARMv8 with LTO, the relocation information is not discarded. Discard it explicitly in the linker script. This fixes LTO build for imx8mm_venice_defconfig. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24ARM: omap3: fix LTO for DM3730 (and possibly other omap3 boards)Marek Behún1-0/+1
Adam Ford says that DM3730 needs board.c compiled without LTO flags. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Adam Ford <aford173@gmail.com>
2021-05-24ARM: fix LTO for rockchip and samsungMarek Behún1-1/+1
When building with LTO, the compiler complains about type mismatch of function usb_gadget_handle_interrupts(). This function is defined without parameters in files arch/arm/mach-rockchip/board.c board/samsung/common/exynos5-dt.c but it should have one parameter, int index. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-05-24ARM: fix LTO for seaboardMarek Behún1-0/+1
When seaboard_defconfig is compiled with LTO, the compiler complains about some instructions not being supported in ARM mode. This is caused by arch/arm/mach-tegra/tegra20/warmboot_avp.c having different CFLAGS declared in Makefile. This file needs to be compiled without LTO. Fix this by removing -flto for this file. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTOMarek Behún1-1/+1
When building imx8mp_evk_defconfig with LTO, the compiler complains about type mismatch of function imx_eqos_txclk_set_rate() in file drivers/net/dwc_eth_qos.c:845:12 which contains a weak definition of this function, vs file arch/arm/mach-imx/imx8m/clock_imx8mm.c which contains an implementation. Change the type of this function in the implementation to fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-24ARM: kona: fix clk_bsc_enable() type mismatch for LTOMarek Behún1-1/+1
When building with LTO, the compiler complains about type mismatch of function clk_bsc_enable() in file: arch/arm/cpu/armv7/kona-common/clk-stubs.c vs other files that define or use this function: warning: type of ‘clk_bsc_enable’ does not match original declaration. Change the type of this function to that of the other usages. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-24ARM: fix LTO for keystoneMarek Behún1-0/+1
When building keystone with LTO the compiler complains: Error: selected processor does not support `smc #0' in Thumb mode Fix this by removing -flto for the file implementing these SMC calls. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-05-24ARM: fix LTO for imx28_xeaMarek Behún2-2/+2
When imx28_xea_defconfig is built with LTO, the compiler complains about the two different declarations of _start: include/asm-generic/sections.h as extern void _start(void); arch/arm/cpu/arm926ejs/mxs/mxs.c as extern uint32_t _start; Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-24ARM: fix LTO build for some thumb-interwork casesMarek Behún2-0/+3
Fix LTO build for some thumb-interwork usecases (such as for da850evm_defconfig), where inline assmebly such as mrc p15,0,r2,c1,c0,0 causes the compiler to fail during LTO linking with Error: selected processor does not support `mrc p15,0,r2,c1,c0,0' in Thumb mode Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24ARM: make gd a function call for LTO and set via set_gd()Marek Behún5-12/+12
On ARM, the gd pointer is stored in registers r9 / x18. For this the -ffixed-r9 / -ffixed-x18 flag is used when compiling, but using global register variables causes errors when building with LTO, and these errors are very difficult to overcome. Richard Biener says [1]: Note that global register vars shouldn't be used with LTO and if they are restricted to just a few compilation units the recommended fix is to build those CUs without -flto. We cannot do this for U-Boot since all CUs use -ffixed-reg flag. It seems that with LTO we could in fact store the gd pointer differently and gain performance or size benefit by allowing the compiler to use r9 / x18. But this would need more work. So for now, when building with LTO, go the clang way, and instead of declaring gd a global register variable, we make it a function call via macro. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68384 Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24ARM: global_data: make set_gd() work for armv5 and armv6Marek Behún1-1/+3
The Thumb instruction `ldr` is able to move high registers only from armv7. For armv5 and armv6 we have to use `mov`. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24sandbox: enable LTO by defaultMarek Behún1-0/+1
Build sandbox targets with LTO by default. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-24sandbox: make LTO availableMarek Behún2-0/+5
Make LTO available for sandbox architecture. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-15 12:42:03 +0000