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2023-03-25efi: Set RUN_64BIT correctly for the EFI appSimon Glass1-2/+2
The U-Boot EFI app can run as a 64-bit program, so set the Kconfig correctly in that case. Make sure it doesn't build SPL, since there is no need to switch from 32 to 64 bit when running. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18event: Correct dependencies on the EVENT frameworkTom Rini1-0/+1
The event framework is just that, a framework. Enabling it by itself does nothing, so we shouldn't ask the user about it. Reword (and correct typos) around this the option and help text. This also applies to DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be visible to the user to select, when EVENT is selected. With this, it's time to address the larger problems. When functionality uses events, typically via EVENT_SPY, the appropriate framework then must be select'd and NOT imply'd. As the functionality will cease to work (and so, platforms will fail to boot) this is non-optional and where select is appropriate. Audit the current users of EVENT_SPY to have a more fine-grained approach to select'ing the framework where used. Also ensure the current users of event_register and also select EVENT_DYNAMIC. Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com> Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com> Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Fixes: 42fdcebf859f ("event: Convert misc_init_f() to use events") Fixes: c5ef2025579e ("dm: fix DM_EVENT dependencies") Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass1-2/+2
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEOSimon Glass1-1/+1
Now that all the old code is gone, rename this option. Driver model migration is now complete. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-07-07spl: Ensure all SPL symbols in Kconfig have some SPL dependencyTom Rini1-0/+1
Tighten up symbol dependencies in a number of places. Ensure that a SPL specific option has at least a direct dependency on SPL. In places where it's clear that we depend on something more specific, use that dependency instead. This means in a very small number of places we can drop redundant dependencies. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28tpl: Ensure all TPL symbols in Kconfig have some TPL dependencyTom Rini1-0/+1
Tighten up symbol dependencies in a number of places. Ensure that a TPL specific option has at least a direct dependency on TPL. In places where it's clear that we depend on something more specific, use that dependency instead. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-01-25x86: Allow any arch to generate ACPI tablesSimon Glass1-9/+0
These have sadly found their way to ARM now. Allow any arch to support generating ACPI tables. Disable this for the tools build. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek1-8/+1
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-02x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROMBin Meng1-2/+0
These 2 options are no longer needed as now binman is used to build u-boot.rom. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Move coreboot sysinfo parsing into generic x86 codeSimon Glass1-0/+21
It is useful to be able to parse coreboot tables on any x86 build which is booted from coreboot. Add a new Kconfig option to enable this feature and move the code so it can be used on any board, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-09x86: Select advanced Intel code only if allowedSimon Glass1-0/+15
At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-09x86: Move INTEL_ACPIGEN to arch/x86Simon Glass1-0/+9
This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Support Atom SoCs using SWSMISCI rather than the SWSCISimon Glass1-0/+6
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add a common routine to write WiFi infoSimon Glass1-0/+8
Intel WiFi chips can use a common routine to write the information needed by linux. Add an implementation of this. Enable it for coral. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Support writing the IntelGraphicsMem tableSimon Glass1-0/+8
This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support external GNVS tablesSimon Glass1-0/+7
At present U-Boot puts a magic number in the ASL for the GNVS table and searches for it later. Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a config for the systemagent PCIEX regions sizeSimon Glass1-0/+18
Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-01x86: Introduce USE_EARLY_BOARD_INIT optionAndy Shevchenko1-0/+3
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. Cc: George McCollister <george.mccollister@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-01x86: rename CONFIG_STACK_SIZEHeinrich Schuchardt1-1/+1
Configuration variables should have the same meaning independent of the architecture. x86 and ARM both use CONFIG_STACK_SIZE: * x86: U-Boot's runtime stack size during reboot * ARM: max stack size that can be used by U-Boot Rename the x86 configuration variable to CONFIG_STACK_SIZE_REBOOT Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-28x86: chromebook_panther: Correct the image layoutSimon Glass1-1/+6
This board does not have microcode but at present that is not supported by Kconfig nor the binman image layout. Fix both of these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28x86: Change how selection of ROMs worksSimon Glass1-0/+4
Most x86 boards build a u-boot.rom which is programmed into SPI flash. But this is not unique to x86. For example some rockchip boards can also boot from SPI flash. Also, at least on x86, binary blobs are sadly quite common. It is not possible to build a functional image without them, and U-Boot needs to know this at build time. Introduce a new CONFIG_HAS_ROM option which selects whether u-boot.rom is built and a new CONFIG_ROM_NEEDS_BLOBS option to indicate whether binary blobs are also needed. If they are not needed, it is safe to build the ROM always. Otherwise we still require the BUILD_ROM environment variable. For now this affects only x86, but future patches will enable this for rockchip too. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20x86: mp: Support APs waiting for instructionsSimon Glass1-0/+7
At present the APs (non-boot CPUs) are inited once and then parked ready for the OS to use them. However in some cases we want to send new requests through, such as to change MTRRs and keep them consistent across CPUs. Change the last state of the flight plan to go into a wait loop, accepting instructions from the main CPU. Drop cpu_map since it is not used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17x86: p2sb: make P2SB driver depend on P2SB uclassWolfgang Wallner1-0/+1
Currently it is possible to select the P2SB driver without selecting the P2SB uclass, which can't work. Fix this by adding a "depends on" in Kconfig. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Add support for ACPI general-purpose eventsSimon Glass1-0/+33
ACPI GPEs are used to signal interrupts from peripherals that are accessed via ACPI. In U-Boot these are modelled as interrupts using a separate interrupt controller. Configuration is via the device tree. Add a simple driver for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07x86: Move P2SB from Apollo Lake to a more generic locationWolfgang Wallner1-0/+7
The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so move its driver to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner1-0/+6
Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add Kconfig and MakefileSimon Glass1-0/+1
Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an option to control the position of SPLSimon Glass1-0/+5
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an option to control the position of U-BootSimon Glass1-0/+5
The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Disable microcode section for FSP2Simon Glass1-0/+4
At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add support for newer CAR schemesSimon Glass1-0/+16
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an option to include a FITSimon Glass1-0/+8
Many Intel SoCs require a FIT in order to boot properly. Add an option to include this and enable it by default. This term can be confused with FIT (Flat Image Tree) in U-Boot so the CONFIG option has to include 'X86'. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Add FSP2 base supportSimon Glass1-2/+50
Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11x86: Drop RESET_SEG_SIZESimon Glass1-5/+0
This is not used anywhere now, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11x86: Update Kconfig options for FSP1Simon Glass1-7/+7
Many of the Kconfig options do not apply to FSP2. Update them to use the FSP_VERSION1 condition instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Change condition for using CARSimon Glass1-0/+8
At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off blocks) are not, since HOBs typically indicate that an FSP is in use, and FSPs handle the CAR init. However this is a bit indirect, and for FSP2 machines which use their own CAR implementation (such as apollolake) but use the FSP for other functions, the logic is wrong. To fix this, add a dedicated Kconfig option to indicate when CAR is used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename existing FSP code to fsp1Simon Glass1-1/+24
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: Add new slimbootloader CPU typePark, Aiden1-0/+9
This slimbootloader CPU type is to enable U-Boot as a payload which runs on top of Slim Bootloader (https://github.com/slimbootloader). The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS booting, and supports QEMU, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP (https://github.com/IntelFsp) for silicon initialization including CAR and memory initialization. The Slim Bootloader generates new HOB (Hand Off Block) which are serial port info, memory map info, performance data info and so on, and passes it to a Payload. U-Boot as a payload will use these HOB information for basic initialization such as serial console. As an initial commit, - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type - Add new arch/x86/cpu/slimbootloader directory with minimum codes - Get hob_list pointer from Slim Bootloader Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-09Fix spelling of available.Vagrant Cascadian1-1/+1
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
2019-05-08x86: Support booting with TPLSimon Glass1-1/+8
Some boards want to use TPL as the first phase of U-Boot. This allows selection of A or B SPL phases, thus allowing the memory init to be upgraded in the field. Add a new Kconfig option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support SPL and TPLSimon Glass1-1/+0
At present only chromebook_link64 supports SPL. It is useful to eb able to support both TPL and SPL to implement verified boot on x86. Enable the options for both along with some suitable default options needed to boot through these phases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10x86: kconfig: Allow board defconfig file to disable 8259 and APICBin Meng1-2/+2
At present the Kconfig options (CONFIG_I8259_PIC and CONFIG_APIC) do not include a prompt message, which makes it impossible to be disabled from a board defconfig file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-10x86: make the LAPIC / IOAPIC construct switchable with KconfigHannes Schmelzer1-0/+9
There are still systems running which do not have any LAPIC or even IOAPIC. Responsible MSRs for those do not exist and the systems are crashing on trying to setup LAPIC. This commit makes the APIC stuff able to switch off for those boards which dont' have an LAPIC / IOAPIC. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-17x86: efi: Refactor the directory of EFI app and payload supportBin Meng1-2/+1
At present the EFI application and payload support codes in the x86 directory is distributed in a hybrid way. For example, the Kconfig options for both app and payload are in arch/x86/lib/efi/Kconfig, but the source codes in the same directory get built only for CONFIG_EFI_STUB. This refactors the codes by consolidating all the EFI support codes into arch/x86/cpu/efi, just like other x86 targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13x86: Conditionally build the pinctrl_ich6 driverBin Meng1-0/+6
The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17pylibfdt: compile pylibfdt only when dtoc/binman is necessaryMasahiro Yamada1-0/+1
Currently, pylibfdt is always compiled if swig is installed on your machine. It is really annoying because most of targets (excepts x86, sunxi, rockchip) do not use dtoc or binman. "checkbinman" and "checkdtoc" are wrong. It is odd that the final build stage checks if we have built necessary tools. If your platform depends on dtoc/binman, you must be able to build pylibfdt. If swig is not installed, it should fail immediately. I added PYLIBFDT, DTOC, BINMAN entries to Kconfig. They should be property select:ed by platforms that need them. Kbuild will descend into scripts/dtc/pylibfdt/ only when CONFIG_PYLIBFDT is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"Bin Meng1-9/+0
This reverts commit 1e6ebee667da47fd3a87839a239a7574c66f5659. It's not appropriate to call the Intel SPI driver specific stuff in the FSP codes. We may add a simple DTS property "intel,spi-lock-down" and let the Intel SPI driver call these stuff instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27x86: Fix ACPI resume dependency to MRC cacheBin Meng1-0/+1
In an S3 resume path, MRC cache is mandatory. Enforce the dependency in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-19x86: Turn off running VGA ROM during S3 resumeBin Meng1-1/+0
This is only needed when graphics console is used. For kernel with native graphics driver, this can be turned off to speed up. Change this option's default to n in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-16x86: Add Intel Braswell SoC supportBin Meng1-0/+1
This adds initial Intel Braswell SoC support. It uses Intel FSP to initialize the chipset. Similar to its predecessor BayTrail, there are some work to do to enable the legacy UART integrated in the Braswell SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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