rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-10-24	riscv: Remove common.h usage	Tom Rini	2	-2/+0
2023-10-19	riscv: remove dram_init_banksize()	Heinrich Schuchardt	1	-16/+0
2023-08-15	common: return type board_get_usable_ram_top	Heinrich Schuchardt	1	-1/+1
2023-07-24	riscv: define a cache line size for the generic CPU	Heinrich Schuchardt	1	-0/+1
2023-07-12	riscv: Rename SiFive CLINT to RISC-V ALINT	Bin Meng	1	-2/+2
2022-09-23	board_f: Fix types for board_get_usable_ram_top()	Pali Rohár	1	-1/+1
2021-05-19	riscv: qemu: Switch to use binman to generate u-boot.itb	Bin Meng	1	-0/+1
2021-05-17	riscv: Split SiFive CLINT support between SPL and U-Boot proper	Bin Meng	1	-1/+2
2021-03-27	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	Simon Glass	1	-1/+1
2021-02-15	Merge branch '2021-02-02-drop-asm_global_data-when-unused'	Tom Rini	1	-0/+1
2021-02-03	riscv: Adjust board_get_usable_ram_top() for 32-bit	Bin Meng	1	-4/+3
2021-02-02	common: Drop asm/global_data.h from common header	Simon Glass	1	-0/+1
2020-09-30	riscv: Rework riscv timer driver to only support S-mode	Sean Anderson	1	-1/+1
2020-05-18	common: Drop net.h from common header	Simon Glass	1	-0/+1
2020-04-23	riscv: qemu: Remove the simple-bus driver for the SoC node	Bin Meng	1	-14/+0
2019-12-02	common: Move board_get_usable_ram_top() out of common.h	Simon Glass	1	-0/+1
2019-12-02	common: Move enable/disable_interrupts out of common.h	Simon Glass	1	-0/+1
2019-08-26	riscv: add SPL support	Lukas Auer	1	-0/+3
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer	1	-1/+1
2019-02-27	riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems	Anup Patel	1	-0/+20
2019-02-27	riscv: Rename cpu/qemu to cpu/generic	Anup Patel	4	-0/+70