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2023-12-21mips: Add a reset_cpu() functionSimon Glass1-1/+7
The current do_reset() is called from a command context. Add a function which can be used from anywhere, as is done on ARM. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-24mips: Remove common.h usageTom Rini3-3/+0
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-06spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LENSimon Glass1-2/+2
Use the new SPL/TPL/VPL_SYS_MALLOC_F symbols to determine whether the malloc pool exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-06-24mips: cpu: Use plain puts() in restart handlerMarek Vasut1-1/+1
This removes dependency on fprintf() , which is not available in SPL unless full printf support is enabled. Signed-off-by: Marek Vasut <marex@denx.de>
2022-07-13mips: add __image_copy_len for SPL linker scriptWeijie Gao1-0/+3
This patch adds __image_copy_len needed by TPL of MT7621 SoC. The __image_copy_len represents the binary blob size of both SPL/TPL binaries. To achieve this, __text_start/end are added for calculation. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-06-23linker_lists: Rename sections to remove . prefixAndrew Scull2-4/+4
Rename the sections used to implement linker lists so they begin with '__u_boot_list' rather than '.u_boot_list'. The double underscore at the start is still distinct from the single underscore used by the symbol names. Having a '.' in the section names conflicts with clang's ASAN instrumentation which tries to add redzones between the linker list elements, causing expected accesses to fail. However, clang doesn't try to add redzones to user sections, which are names with all alphanumeric and underscore characters. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-06Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini1-6/+2
- Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR - Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack pointer directly, otherwise we use the common calculation. - On some platforms that were using the standard calculation but did not set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them. - On a small number of platforms that were not subtracting GENERATED_GBL_DATA_SIZE do so now via the standard calculation. - CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most board config header files. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31Convert CONFIG_SKIP_LOWLEVEL_INIT et al to KconfigTom Rini1-2/+2
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-24mips: enable _machine_restart for splWeijie Gao1-1/+1
The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage. Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a chance to use _machine_restart instead of the sysreset driver. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-11-30mips: start.S: Add Octeon boot header compatibilityStefan Roese1-2/+8
Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-18mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init codeStefan Roese1-0/+5
This patch adds the optional call to mips_mach_early_init() to start.S at a very early stage. Its disabled per default. It can be used for very early machine / platform specific init code. Its called very early and at this stage the PC is allowed to differ from the linking address (CONFIG_TEXT_BASE) as no absolute jump has been performed until this call. It will be used by thje Octeon platform. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-18mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck1-1/+1
Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: add config options for generic cache setup codeDaniel Schwierzeck1-1/+5
Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: refactor disabling of cachesDaniel Schwierzeck1-5/+4
Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: start.S: remove dead codeDaniel Schwierzeck1-9/+0
Since commit 703ec9ddf965 ("MIPS: Stop building position independent code") the relocation code was completely reworked and removed from start.S. Remove some left-overs of the old code. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: time: Only compile the weak get_tbclk() when neededStefan Roese1-0/+2
This patch opts-out the compilation of get_tbclk() if CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon platform, where the weak get_tbclk() function is overwritten by its platform specific one. Signed-off-by: Stefan Roese <sr@denx.de>
2020-05-18command: Remove the cmd_tbl_t typedefSimon Glass1-1/+1
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-27mips: add a option to support not reserving malloc space on initial stackWeijie Gao1-2/+4
The initial stack on some platforms is too small to hold a large malloc space. This patch adds a option to allow these platforms not reserving the malloc space on initial stack. These platforms should set the malloc base after DRAM is usable. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27mips: add an option to support initialize SRAM for initial stackWeijie Gao1-0/+7
Currently CONFIG_MIPS_INIT_STACK_IN_SRAM assumes the memory space for the initial stack can be used directly. However on some platform the SRAM needs initialization, e.g. lock cache. This patch adds an option to allow a new function mips_sram_init() being called before setup_stack_gd. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27mips: add an option to enable u_boot_list section for SPL loaders in ↵Weijie Gao1-1/+1
u-boot-spl.lds u_boot_list is not only used by DM, but also by some SPL image load methods such as spl_nor.c. This patch adds an option CONFIG_SPL_LOADER_SUPPORT in conjunction with CONFIG_SPL_DM surrounding the u_boot_list section to make sure SPL image loaders can be correctly built into u-boot SPL without DM enabled. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27mips: enable support for appending dtb to spl binaryWeijie Gao1-0/+2
If CONFIG_SPL_OF_CONTROL is enabled for SPL and CONFIG_OF_SEPARATE is also enabled, the dtb will be appended to the u-boot-spl.bin. When calling dm_init_and_scan() in SPL, fdtdec_setup() will try to locate dtb at the end of u-boot-spl.bin, by referencing to _image_binary_end. However _image_binary_end is currently missing in u-boot-spl.lds. This patch adds _image_binary_end to u-boot-spl.lds to make sure linking u-boot-spl will not fail. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27mips: start.S: avoid overwriting outside gd when clearing global data in stackWeijie Gao1-1/+2
When setting up initial stack, global data will also be put in the stack, and being cleared. The assembler instructions for clearing gd is as follows: move t0, k0 1: PTR_S zero, 0(t0) blt t0, t1, 1b PTR_ADDIU t0, PTRSIZE t0 is the start address of gd, t1 is the end address of gd (t0 + GD_SIZE). [PTR_ADDIU t0, PTRSIZE] is in the delay slot of [blt t0, t1, 1b], so it will be executed before the branch operation. However the comparison for the BLT instruction is done before executing the delay slot. This means when the last word just before k1 is cleared, the loop will continue to run once. This will clear an extra word at k1, which is outside the global data. Global data is placed at the top of the stack. If the initial stack is a SRAM or locked cache, the area outside them may be inaccessible. A write operation performed in this area may cause an exception. To solve this, [PTR_ADDIU t0, PTRSIZE] should be placed before the BLT instruction. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-09MIPS: allow override of get_tbclk()Alex Nemirovsky1-1/+1
Allow SoC or board layers with reconfigurable cpu clocks capabilties to do implementation specific lookups and service get_tbclk() requests. Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-01-17common: Move get_tbclk() to time.hSimon Glass1-0/+1
This function related to timer and most of the timer functions are in time.h, so move this function there. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-02common: Move interrupt functions into a new headerSimon Glass1-0/+1
These functions do not use driver model but are fairly widely used in U-Boot. But it is not clear that they will use driver model anytime soon, so we don't want to label them as 'legacy'. Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it is widely used in U-Boot already. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-26linker: Modify linker scripts to be more genericTom Rini1-2/+2
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE. This lets us re-use the same script for both SPL and TPL. Add logic to scripts/Makefile.spl to pass in the right value when preprocessing the script. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-16MIPS: optimize and fix ELF sectionsDaniel Schwierzeck2-68/+136
Discard ABI related sections which are not required for debugging. Rearrange debug sections similar to Linux. Remove the remaining explicitely specified sections in the unused part because those sections are not created anymore or because the linker puts them by default at the end of the ELF binary. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
2018-12-19MIPS: move create_tlb() in an proper header: mipsregs.hGregory CLEMENT1-10/+0
Export create_tlb() as an inline function in mipsregs.h. It allows to remove the declaration of the function from the board files. Then it will allow also to use this function very early in the boot when the stack is not usable. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-11-18MIPS: fix linking of standalone programsDaniel Schwierzeck2-14/+0
Use the global MIPS specific u-boot.lds for linking standalone programs instead of the outdated ones in examples/standalone/. Also pass --gc-sections in LDFLAGS_STANDALONE to optimize the size of standalone programs. Finally remove the deprecated config.mk files in arch/mips/cpu/mips[32,64]/. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18Kbuild: add LDFLAGS_STANDALONEDaniel Schwierzeck2-4/+4
Introduce a new Makefile variable for passing LDFLAGS to standalone programs. Currently the variable CONFIG_STANDALONE_LOAD_ADDR is misued on some archs to pass a specific linker script. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-02MIPS: make size of relocation table fixed but configurableDaniel Schwierzeck1-7/+13
Currently the size of the relocation table will be shrunk to the actual size needed. Although this gives a maximal space saving, it messes up the _end symbol. This breaks features like appended DTBs because the _end symbol doesn't point to the real end of the U-Boot binary. Remove the size shrinking and make the size of the relocation table fixed but configurable. This follows the Linux approach and the user can adjust the size to his needs. Also rename the relocation table section from .rel to .data.reloc to follow the Linux approach and to avoid ambiguities with the .rel.* sections added by the linker. Reported-by: Lars Povlsen <lars.povlsen@microsemi.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22MIPS: start.S: make boot config at offset 0x10 configurableDaniel Schwierzeck1-16/+5
Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini10-24/+10
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-28MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.ldsPaul Burton1-6/+0
The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to 2 or 3 for 32 bit or 64 bit builds respectively. This macro is never actually used though, so remove the dead code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-27mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan1-3/+3
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-25MIPS: Stop building position independent codePaul Burton2-162/+9
U-Boot has up until now built with -fpic for the MIPS architecture, producing position independent code which uses indirection through a global offset table, making relocation fairly straightforward as it simply involves patching up GOT entries. Using -fpic does however have some downsides. The biggest of these is that generated code is bloated in various ways. For example, function calls are indirected through the GOT & the t9 register: 8f998064 lw t9,-32668(gp) 0320f809 jalr t9 Without -fpic the call is simply: 0f803f01 jal be00fc04 <puts> This is more compact & faster (due to the lack of the load & the dependency the jump has on its result). It is also easier to read & debug because the disassembly shows what function is being called, rather than just an offset from gp which would then have to be looked up in the ELF to discover the target function. Another disadvantage of -fpic is that each function begins with a sequence to calculate the value of the gp register, for example: 3c1c0004 lui gp,0x4 279c3384 addiu gp,gp,13188 0399e021 addu gp,gp,t9 Without using -fpic this sequence no longer appears at the start of each function, reducing code size considerably. This patch switches U-Boot from building with -fpic to building with -fno-pic, in order to gain the benefits described above. The cost of this is an extra step during the build process to extract relocation data from the ELF & write it into a new .rel section in a compact format, plus the added complexity of dealing with multiple types of relocation rather than the single type that applied to the GOT. The benefit is smaller, cleaner, more debuggable code. The relocate_code() function is reimplemented in C to handle the new relocation scheme, which also makes it easier to read & debug. Taking maltael_defconfig as an example the size of u-boot.bin built using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils 2.24.90) shrinks from 254KiB to 224KiB. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-05-10MIPS: add initial infrastructure for Broadcom MIPS SoCsÁlvaro Fernández Rojas1-0/+5
CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: allow using generic sysreset driversÁlvaro Fernández Rojas1-0/+2
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10MIPS: call debug_uart_init right before board_init_fDaniel Schwierzeck1-0/+14
All MIPS boards that support debug uart are calling debug_uart_init right at the beginning of board_early_init_f. Instead of doing that, let's provide a generic call to debug_uart_init right before the call to board_init_f if debug uart is enabled for boards without stack in SRAM. On the other hand, boards with stack in SRAM can call earlier (right before low level init). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2016-11-30MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck1-0/+7
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: factor out code for initial stack and global dataDaniel Schwierzeck1-26/+30
Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck1-24/+50
Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix ROM exception vectorsDaniel Schwierzeck1-10/+19
When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck1-3/+8
This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-21MIPS: Hang if run on a secondary CPUPaul Burton1-1/+20
Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Fix cache maintenance in relocate_code & simplifyPaul Burton2-26/+21
The relocate_code function was handling cache maintenance incorrectly. It copied U-Boot to its new location, flushed the caches & then proceeded to apply relocations & jump to the new code without flushing the caches again. This is problematic as the instruction cache could potentially have already fetched instructions that hadn't had relocs applied. Rework this to perform the flush_cache call using the code in the original copy of U-Boot, after having applied relocations to the new copy of U-Boot. The new U-Boot can then be jumped to safely once that cache flush has been performed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Ensure Config.K0=2 applies before any memory accessesPaul Burton1-0/+1
During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Map CM Global Control RegistersPaul Burton3-0/+53
Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: If we don't need DDR for cache init, init cache firstPaul Burton1-0/+9
On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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