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authorDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2020-07-12 00:45:57 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2020-07-18 14:23:25 +0200
commit57bfb1aed6a87b19ca7e2a76df83ea387621e2e9 (patch)
tree95d4f1feb7215133cd9d1e06f4e65abd7f56a68b /arch/mips/cpu
parent60772433dd42987f3b965188d9577150084b8956 (diff)
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mips: add config options for generic cache setup code
Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/mips/cpu')
-rw-r--r--arch/mips/cpu/start.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index a9f8743..0c30303 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -195,7 +195,7 @@ wr_done:
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
mtc0 zero, CP0_COMPARE
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_MIPS_CACHE_DISABLE
/* Disable caches */
PTR_LA t9, mips_cache_disable
jalr t9
@@ -234,12 +234,16 @@ wr_done:
jalr t9
nop
# endif
+#endif
+#ifdef CONFIG_MIPS_CACHE_SETUP
/* Initialize caches... */
PTR_LA t9, mips_cache_reset
jalr t9
nop
+#endif
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init