Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2023-03-09 | xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write | Algapally Santosh Sagar | 1 | -6/+1 |
2023-01-16 | xilinx: versal-net: Add support for timer and start it | Ashok Reddy Soma | 2 | -0/+42 |
2022-11-22 | soc: xilinx: versal-net: Add soc_xilinx_versal_net driver | Michal Simek | 1 | -0/+5 |
2022-09-26 | spi: cadence_qspi: Add support for Versal NET platform | Michal Simek | 1 | -0/+4 |
2022-09-26 | arm64: versal-net: Add support for Versal NET platform | Michal Simek | 6 | -0/+220 |