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2021-09-03Revert most of the series for adding vexpress_aemv8r supportWIP/03Sep2021-nextTom Rini3-102/+0
Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-02psci: fix double declarationOleksandr Suvorov1-1/+0
The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott <mike@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2021-09-02armv8: Add ARMv8 MPU configuration logicPeter Hoyes1-0/+61
Armv8r64 is the first Armv8 platform that only has a PMSA at the current exception level. The architecture supplement for Armv8r64 describes new fields in ID_AA64MMFR0_EL1 which can be used to detect whether a VMSA or PMSA is present. These fields are RES0 on Armv8a. Add logic to read these fields and, for the protection of the memory used by U-Boot, initialize the MPU instead of the MMU during init, then clear the MPU regions before transition to the next stage. Provide a default (blank) MPU memory map, which can be overridden by board configurations. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02armv8: Ensure EL1&0 VMSA is enabledPeter Hoyes2-0/+41
On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02armv8: Disable pointer authentication traps for EL1Peter Hoyes2-2/+24
The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-08-31Convert CONFIG_SKIP_LOWLEVEL_INIT et al to KconfigTom Rini1-1/+1
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30arm: Migrate GICV2 / GICV3 to KconfigTom Rini1-2/+0
Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig. We still have the GIC related registers that need to be handled more cleanly but start by moving this symbol to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30Convert CONFIG_SYS_I2C_EARLY_INIT to KconfigTom Rini1-3/+0
Convert SYS_I2C_EARLY_INIT to Kconfig, and make it depend on SPL_SYS_I2C_LEGACY. Remove the weak implementation as it's either something that needs to exist for real, or shouldn't be called. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30Convert CONFIG_SYS_I2C_LEGACY to Kconfig and add CONFIG_[ST]PL_SYS_I2C_LEGACYTom Rini1-1/+0
First, we convert CONFIG_SYS_I2C_LEGACY to Kconfig. Next, as you cannot have SYS_I2C_LEGACY and DM_I2C at the same time, introduce CONFIG_SPL_SYS_I2C_LEGACY so that we can enable the legacy option only in SPL. Finally, for some PowerPC cases we also need CONFIG_TPL_SYS_I2C_LEGACY support. Convert all of the existing users to one or more symbols. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-09imx8ulp: add upower api supportPeng Fan1-0/+15
Add upower api support, this is modified from upower firmware exported package. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: move struct mu_type to common headerPeng Fan1-0/+25
Move struct mu_type to common header to make it reusable by upower and S400 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add iomuxc supportPeng Fan1-0/+82
Add i.MX8ULP iomuxc support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: iMX8ULP: Add boot device relevant functionsYe Li1-0/+1
Read from ROM API to get current boot device. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: unify rdc functionsPeng Fan1-0/+27
Unify rdc function to rdc.c Update soc.c to use new rdc function Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add rdc supportPeng Fan1-0/+2
There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: release and configure XRDC at early phaseYe Li1-0/+12
Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09drivers: misc: s400_api: Update API for fuse read and writeYe Li1-1/+6
Add API to support fuse read and write Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Update S400 API for release RDCYe Li1-1/+1
The RDC API is updated to add a field for XRDC or TRDC Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Add S400 API for image authenticationYe Li1-1/+7
Add S400 API for image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add clock supportPeng Fan4-1/+278
Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09driver: misc: Add MU and S400 API to communicate with SentinelYe Li2-0/+35
Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx8ulp: add container supportYe Li3-1/+5
i.MX8ULP support using ROM API to load container image, it use same ROM API as i.MX8MN/MP, and use same container format as i.MX8QM/QXP. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8: Move container image header file to mach-imxYe Li1-0/+0
Since the container is shared among i.MX platforms, move its header file to mach-imx Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: basic i.MX8ULP supportPeng Fan5-0/+288
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: support print cpu infoPeng Fan1-0/+3
Support print cpu info. the clock function has not been added, it will be added in following patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: sys_proto: move boot mode define to common headerPeng Fan2-9/+10
These defines could be reused by i.MX8ULP, so move them to common header. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: add i.MX8ULP cpu type and helperPeng Fan3-0/+16
Add i.MX8ULP cpu type and helpers. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-07-31Merge https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini1-0/+11
- Move the PSCI runtime code for H3/A23/A33 into SRAM - Pick the environment from the actual MMC boot device (SD card vs. eMMC) - Plus a small improvement from Icenowy, just for good measure.
2021-08-01sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2Samuel Holland1-0/+11
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure monitor code (providing PSCI runtime services). And while those SoCs do not have the secure SRAM B like older SoCs, there is enough (secure) SRAM A2 to put the monitor code and data in there instead. Follow the design of 64-bit SoCs and use the first part for the monitor, and the last 16 KiB for the SCP firmware. With this change, the monitor no longer needs to reserve a region in DRAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: amend commit message, fix R40 and V3s build] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-28arm64: Update memcpy_{from, to}io() helpersPatrice Chotard1-10/+15
At early U-Boot stage, before relocation, MMU is not yet configured and disabled. DDR may not be configured with the correct memory attributes (can be configured in MT_DEVICE instead of MT_MEMORY). In this case, usage of memcpy_{from, to}io() may leads to synchronous abort in AARCH64 in case the normal memory address is not 64Bits aligned. To avoid such situation, forbid usage of normal memory cast to (u64 *) in case MMU is not enabled. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: mark.kettenis@xs4all.nl Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-28i2c: Rename CONFIG_SYS_I2C to CONFIG_SYS_I2C_LEGACYSimon Glass1-1/+1
It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less than a year away. Also we want to have a CONFIG_I2C for U-Boot proper just like we have CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules. Rename this symbol so it is clear it is going away. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-23armv8: Initialize CNTFRQ if at highest exception levelPeter Hoyes2-0/+24
CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-07-19Merge tag 'ti-v2021.10-rc1' of ↵Tom Rini2-2/+63
https://source.denx.de/u-boot/custodians/u-boot-ti - Enabled distro boot for all TI platforms. - Cleanup for AM335x Guardian Board - PRUSS rproc on AM65 platform. - Add PMIC support for J7200 - Misc fixes for Nokia RX-51 # Conflicts: # arch/arm/mach-omap2/am33xx/Kconfig
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵WIP/17Jul2021Tom Rini2-1/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17arm: imx8mq: Add USB clock init functionYe Li1-0/+1
Add clock function to setup relevant clocks for USB3.0 controllers and PHYs on i.MX8MQ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-15arm: omap3: Make secureworld_exit() staticAdam Ford1-1/+0
secureworld_exit() is only used in one file, so make it static to that file and remove it from sys_proto.h. This may help with some further optimization in the future. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210625192308.277136-3-aford173@gmail.com
2021-07-15arm: omap3: Make try_unlock_memory() staticAdam Ford1-1/+0
try_unlock_memory() is only used in one file, so make it static in that file,remove it from the sys_proto header file, and relocate it into the #ifdef section that call it. This will make it only built under the conditions when it is called, and it may help with some further optimization in the future. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210625192308.277136-2-aford173@gmail.com
2021-07-15am335x, guardian: mem: Add board dependent mem valuesMoses Christopher1-0/+63
- Add mem-guardian.h derived from am33xx/mem.h * Add GPMC config values optimized for Bosch Guardian Board * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210611161350.2141-3-Gireesh.Hiremath@in.bosch.com
2021-07-10pci: imx: use reset-gpios if defined by device-treeTim Harvey1-1/+2
If reset-gpio is defined by device-tree use that if CONFIG_PCIE_IMX_PERST_GPIO is not defined. Note that after this the following boards which define CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without consequence: - mx6sabresd - mx6sxsabresd - novena - tbs2910 - vining_2000 Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does not have reset-gpios defined it it's pcie node in the dt thus removing CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds reset-gpios. Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD) Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD) Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD) Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD) Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD) Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD) Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10mmc: sunxi: Increase MMIO FIFO read performanceAndre Przywara1-0/+1
To avoid the complexity of DMA operations (with chained descriptors), we use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us to drain or fill the MMC data buffer FIFO very easily. However those MMIO accesses are somewhat costly, so this limits our MMC performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6 (partly due to the lower AHB1 frequency). As it turns out we read the FIFO status register after *every* word we read or write, which effectively doubles the number of MMIO accesses, thus effectively more than halving our performance. To avoid this overhead, we can make use of the FIFO level bits, which are in the very same FIFO status registers. So for a read request, we now can collect as many words as the FIFO level originally indicated, and only then need to update the status register. We don't know for sure the size of the FIFO (and it seems to differ across SoCs anyway), so writing is more fragile, which is why we still use the old method for that. If we find a minimum FIFO size available on all SoCs, we could use that, in a later optimisation. This patch increases the eMMC read speed on a Pine64-LTS from about 22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s we now reach the practical limit for 3.3V SD cards. On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10mmc: sunxi: Fix MMC clock parent selectionAndre Przywara1-1/+1
Most Allwinner SoCs which use the so called "new timing mode" in their MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their parent input clock. This is interestingly enough compensated by a hidden "by 2" post-divider in the mod clock, so the divider and actual output rate stay the same. Even though for the H6 and H616 (but only for them!) we use the doubled input clock for the divider computation, we never accounted for the implicit post-divider, so the clock was only half the speed on those SoCs. This didn't really matter so far, as our slow MMIO routine limits the transfer speed anyway, but we will fix this soon. Clean up the code around that selection, to always use the normal PLL6 (PERIPH0(1x)) clock as an input. As the rate and divider are the same, that makes no difference. Explain the hardware differences in a comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10sunxi: clock: H6/H616: Fix PLL clock factor encodingsAndre Przywara1-2/+2
Most clock factors and dividers in the H6 PLLs use a "+1 encoding", which we were missing on two occasions. This fixes the MMC clock setup on the H6, which could be slightly off due to the wrong parent frequency: mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 Also the CPU frequency (PLL1) was a tad too high before. For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code itself, not in the bit field macro. Move this there to be aligned with what the other SoCs and other PLLs do. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2021-07-07arm: Remove spear600 boards and the rest of SPEAr supportTom Rini9-553/+0
These boards have not been converted to CONFIG_DM_USB by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the last of the SPEAr platforms, so remove the rest of the remaining support as well. Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07arm: Remove spear320 boardsTom Rini2-12/+1
These boards have not been converted to CONFIG_DM_USB by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is also the last SPEAR3XX platform, remove that symbol as well. Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07arm: Remove spear310 boardsTom Rini1-16/+0
These boards have not been converted to CONFIG_DM_USB by the deadline and is also missing conversion to CONFIG_DM. Remove them. Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07arm: Remove spear300 boardsTom Rini1-3/+0
These boards have not been converted to CONFIG_DM_USB by the deadline and is also missing conversion to CONFIG_DM. Remove them. Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-06lpc32xx: Kconfig: switch to CONFIG_CONS_INDEXTrevor Woerner1-2/+2
There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefsMasami Hiramatsu1-7/+1
Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_XXXX) in asm/gpio.h. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini4-0/+13
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
2021-06-23global_data: Ensure we have <config.h> when symbols are not in Kconfig yetTom Rini1-0/+2
All symbols that are defined in Kconfig will always be defined (or not) prior to preprocessing due to the -include directive while building. However, symbols which are not yet migrated will only be defined (or not) once the board config.h is included, via <config.h>. While the end goal must be to migrate all symbols, today we have cases where the size of gd will get mismatched within the build, based on include order. Mitigate this by making sure that any <asm/global_data.h> that uses symbols not in Kconfig does start with <config.h>. Remove this when not needed. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Huan Wang <alison.wang@nxp.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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