diff options
Diffstat (limited to 'drivers/net')
52 files changed, 2212 insertions, 120 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b4ff033..e7d0ddf 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -243,6 +243,13 @@ config DWC_ETH_QOS_IMX The Synopsys Designware Ethernet QOS IP block with the specific configuration used in IMX soc. +config DWC_ETH_QOS_INTEL + bool "Synopsys DWC Ethernet QOS device support for Intel" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with the specific + configuration used in the Intel Elkhart-Lake soc. + config DWC_ETH_QOS_ROCKCHIP bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs" depends on DWC_ETH_QOS @@ -325,6 +332,14 @@ config EEPRO100 This driver supports Intel(R) PRO/100 82557/82559/82559ER fast ethernet family of adapters. +config ESSEDMA + bool "Qualcomm ESS Edma support" + depends on DM_ETH && ARCH_IPQ40XX + select PHYLIB + help + This driver supports ethernet DMA adapter found in + Qualcomm IPQ40xx series SoC-s. + config ETH_SANDBOX depends on SANDBOX default y @@ -453,6 +468,7 @@ config FTMAC100 config FTGMAC100 bool "Ftgmac100 Ethernet Support" select PHYLIB + depends on NET help This driver supports the Faraday's FTGMAC100 Gigabit SoC Ethernet controller that can be found on Aspeed SoCs (which diff --git a/drivers/net/Makefile b/drivers/net/Makefile index dce7168..4946a63 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o +obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o @@ -29,6 +30,7 @@ obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o +obj-$(CONFIG_ESSEDMA) += essedma.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c index f2e4392..2e1f3cd 100644 --- a/drivers/net/aspeed_mdio.c +++ b/drivers/net/aspeed_mdio.c @@ -113,6 +113,7 @@ static int aspeed_mdio_probe(struct udevice *dev) static const struct udevice_id aspeed_mdio_ids[] = { { .compatible = "aspeed,ast2600-mdio" }, + { .compatible = "aspeed,ast2700-mdio" }, { } }; diff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h index 477667f..ac5e45d 100644 --- a/drivers/net/bcm-sf2-eth-gmac.h +++ b/drivers/net/bcm-sf2-eth-gmac.h @@ -18,7 +18,6 @@ #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) - #define GMAC_DMA_PTR_OFFSET 0x04 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c index 25fbcd7..96e804e 100644 --- a/drivers/net/bnxt/bnxt.c +++ b/drivers/net/bnxt/bnxt.c @@ -3,7 +3,6 @@ * Copyright 2019-2021 Broadcom. */ - #include <asm/io.h> #include <dm.h> #include <linux/delay.h> diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 918a386..e47101c 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -64,7 +64,6 @@ struct eth_mac_regs { #define MII_REGMSK (0x1F << 6) #define MII_ADDRMSK (0x1F << 11) - struct eth_dma_regs { u32 busmode; /* 0x00 */ u32 txpolldemand; /* 0x04 */ diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 67ac86f..3415c41 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -32,6 +32,7 @@ #include <clk.h> #include <cpu_func.h> #include <dm.h> +#include <dm/device_compat.h> #include <errno.h> #include <eth_phy.h> #include <log.h> @@ -50,6 +51,7 @@ #include <asm/arch/clock.h> #include <asm/mach-imx/sys_proto.h> #endif +#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/printk.h> @@ -146,6 +148,25 @@ static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 1000000, true); } +/* Bitmask common for mdio_read and mdio_write */ +#define EQOS_MDIO_BITFIELD(pa, rda, cr) \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_PA_MASK, pa) | \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_RDA_MASK, rda) | \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_CR_MASK, cr) | \ + EQOS_MAC_MDIO_ADDRESS_GB + +static u32 eqos_mdio_bitfield(struct eqos_priv *eqos, int addr, int devad, int reg) +{ + int cr = eqos->config->config_mac_mdio; + bool c22 = devad == MDIO_DEVAD_NONE ? true : false; + + if (c22) + return EQOS_MDIO_BITFIELD(addr, reg, cr); + else + return EQOS_MDIO_BITFIELD(addr, devad, cr) | + EQOS_MAC_MDIO_ADDRESS_C45E; +} + static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg) { @@ -163,15 +184,17 @@ static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, } val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_READ << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; + val &= EQOS_MAC_MDIO_ADDRESS_SKAP; + + val |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, + EQOS_MAC_MDIO_ADDRESS_GOC_READ); + + if (val & EQOS_MAC_MDIO_ADDRESS_C45E) { + writel(FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg), + &eqos->mac_regs->mdio_data); + } + writel(val, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); @@ -194,7 +217,8 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg, u16 mdio_val) { struct eqos_priv *eqos = bus->priv; - u32 val; + u32 v_addr; + u32 v_data; int ret; debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, @@ -206,20 +230,19 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, return ret; } - writel(mdio_val, &eqos->mac_regs->mdio_data); + v_addr = readl(&eqos->mac_regs->mdio_address); + v_addr &= EQOS_MAC_MDIO_ADDRESS_SKAP; - val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; - writel(val, &eqos->mac_regs->mdio_address); + v_addr |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, + EQOS_MAC_MDIO_ADDRESS_GOC_WRITE); + v_data = mdio_val; + if (v_addr & EQOS_MAC_MDIO_ADDRESS_C45E) + v_data |= FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg); + + writel(v_data, &eqos->mac_regs->mdio_data); + writel(v_addr, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); ret = eqos_mdio_wait_idle(eqos); @@ -1279,6 +1302,13 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + pr_err("eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); + ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); if (ret) { pr_err("reset_get_by_name(rst) failed: %d\n", ret); @@ -1353,6 +1383,69 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) return 0; } +static int eqos_bind(struct udevice *dev) +{ + static int dev_num; + const size_t name_sz = 16; + char name[name_sz]; + + /* Device name defaults to DT node name. */ + if (ofnode_valid(dev_ofnode(dev))) + return 0; + + /* Assign unique names in case there is no DT node. */ + snprintf(name, name_sz, "eth_eqos#%d", dev_num++); + return device_set_name(dev, name); +} + +/* + * Get driver data based on the device tree. Boards not using a device tree can + * overwrite this function. + */ +__weak void *eqos_get_driver_data(struct udevice *dev) +{ + return (void *)dev_get_driver_data(dev); +} + +static fdt_addr_t eqos_get_base_addr_common(struct udevice *dev, fdt_addr_t addr) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + if (addr == FDT_ADDR_T_NONE) { +#if CONFIG_IS_ENABLED(FDT_64BIT) + dev_err(dev, "addr=0x%llx is invalid.\n", addr); +#else + dev_err(dev, "addr=0x%x is invalid.\n", addr); +#endif + return -EINVAL; + } + + eqos->regs = addr; + eqos->mac_regs = (void *)(addr + EQOS_MAC_REGS_BASE); + eqos->mtl_regs = (void *)(addr + EQOS_MTL_REGS_BASE); + eqos->dma_regs = (void *)(addr + EQOS_DMA_REGS_BASE); + + return 0; +} + +int eqos_get_base_addr_dt(struct udevice *dev) +{ + fdt_addr_t addr = dev_read_addr(dev); + return eqos_get_base_addr_common(dev, addr); +} + +int eqos_get_base_addr_pci(struct udevice *dev) +{ + fdt_addr_t addr; + void *paddr; + + paddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); + addr = paddr ? (fdt_addr_t)paddr : FDT_ADDR_T_NONE; + + return eqos_get_base_addr_common(dev, addr); +} + static int eqos_probe(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1361,17 +1454,12 @@ static int eqos_probe(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); eqos->dev = dev; - eqos->config = (void *)dev_get_driver_data(dev); - eqos->regs = dev_read_addr(dev); - if (eqos->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed\n"); + eqos->config = eqos_get_driver_data(dev); + if (!eqos->config) { + pr_err("Failed to get driver data.\n"); return -ENODEV; } - eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); - eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); - eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); - eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); @@ -1552,6 +1640,7 @@ U_BOOT_DRIVER(eth_eqos) = { .name = "eth_eqos", .id = UCLASS_ETH, .of_match = of_match_ptr(eqos_ids), + .bind = eqos_bind, .probe = eqos_probe, .remove = eqos_remove, .ops = &eqos_ops, diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8b3d0d4..ce57e22 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -3,8 +3,11 @@ * Copyright 2022 NXP */ -#include <phy_interface.h> +#include <asm/gpio.h> +#include <clk.h> #include <linux/bitops.h> +#include <phy_interface.h> +#include <reset.h> /* Core registers */ @@ -79,19 +82,20 @@ struct eqos_mac_regs { #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3 -#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 -#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 -#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define EQOS_MAC_MDIO_ADDRESS_PA_MASK GENMASK(25, 21) +#define EQOS_MAC_MDIO_ADDRESS_RDA_MASK GENMASK(20, 16) +#define EQOS_MAC_MDIO_ADDRESS_CR_MASK GENMASK(11, 8) #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) -#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 +#define EQOS_MAC_MDIO_ADDRESS_GOC_MASK GENMASK(3, 2) #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) +#define EQOS_MAC_MDIO_DATA_RA_MASK GENMASK(31, 16) #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff #define EQOS_MTL_REGS_BASE 0xd00 @@ -285,7 +289,10 @@ void eqos_inval_desc_generic(void *desc); void eqos_flush_desc_generic(void *desc); void eqos_inval_buffer_generic(void *buf, size_t size); void eqos_flush_buffer_generic(void *buf, size_t size); +int eqos_get_base_addr_dt(struct udevice *dev); +int eqos_get_base_addr_pci(struct udevice *dev); int eqos_null_ops(struct udevice *dev); +void *eqos_get_driver_data(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index d6bed27..6424328 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -47,6 +47,12 @@ static int eqos_probe_resources_imx(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_dbg(dev, "eqos_get_base_addr_dt failed: %d", ret); + goto err_probe; + } + interface = eqos->config->interface(dev); if (interface == PHY_INTERFACE_MODE_NA) { diff --git a/drivers/net/dwc_eth_qos_intel.c b/drivers/net/dwc_eth_qos_intel.c new file mode 100644 index 0000000..a2c6825 --- /dev/null +++ b/drivers/net/dwc_eth_qos_intel.c @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2024 DENX Software Engineering GmbH + * Philip Oberfichtner <pro@denx.de> + * + * Based on linux v6.6.39, especially drivers/net/ethernet/stmicro/stmmac + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <miiphy.h> +#include <net.h> +#include <pci.h> + +#include "dwc_eth_qos.h" +#include "dwc_eth_qos_intel.h" + +static struct pci_device_id intel_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII2G5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5) }, + {} +}; + +static int pci_config(struct udevice *dev) +{ + u32 val; + + /* Try to enable I/O accesses and bus-mastering */ + dm_pci_read_config32(dev, PCI_COMMAND, &val); + val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + dm_pci_write_config32(dev, PCI_COMMAND, val); + + /* Make sure it worked */ + dm_pci_read_config32(dev, PCI_COMMAND, &val); + if (!(val & PCI_COMMAND_MEMORY)) { + dev_err(dev, "%s: Can't enable I/O memory\n", __func__); + return -ENOSPC; + } + + if (!(val & PCI_COMMAND_MASTER)) { + dev_err(dev, "%s: Can't enable bus-mastering\n", __func__); + return -EPERM; + } + + return 0; +} + +static void limit_fifo_size(struct udevice *dev) +{ + /* + * As described in Intel Erratum EHL22, Document Number: 636674-2.1, + * the PSE GbE Controllers advertise a wrong RX and TX fifo size. + * Software should limit this value to 64KB. + */ + struct eqos_priv *eqos = dev_get_priv(dev); + + eqos->tx_fifo_sz = 0x8000; + eqos->rx_fifo_sz = 0x8000; +} + +static int serdes_status_poll(struct udevice *dev, + unsigned char phyaddr, unsigned char phyreg, + unsigned short mask, unsigned short val) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned int retries = 10; + unsigned short val_rd; + + do { + miiphy_read(eqos->mii->name, phyaddr, phyreg, &val_rd); + if ((val_rd & mask) == (val & mask)) + return 0; + udelay(POLL_DELAY_US); + } while (--retries); + + return -ETIMEDOUT; +} + + /* Returns -ve if MAC is unknown and 0 on success */ +static int mac_check_pse(const struct udevice *dev, bool *is_pse) +{ + struct pci_child_plat *plat = dev_get_parent_plat(dev); + + if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL) + return -ENXIO; + + switch (plat->device) { + case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5: + *is_pse = 1; + return 0; + + case PCI_DEVICE_ID_INTEL_EHL_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_SGMII1: + case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5: + *is_pse = 0; + return 0; + }; + + return -ENXIO; +} + +/* Check if we're in 2G5 mode */ +static bool serdes_link_mode_2500(struct udevice *dev) +{ + const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR; + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned short data; + + miiphy_read(eqos->mii->name, phyad, SERDES_GCR, &data); + if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) + return true; + + return false; +} + +static int serdes_powerup(struct udevice *dev) +{ + /* Based on linux/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c */ + + const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR; + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned short data; + int ret; + bool is_pse; + + /* Set the serdes rate and the PCLK rate */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + + data &= ~SERDES_RATE_MASK; + data &= ~SERDES_PCLK_MASK; + + if (serdes_link_mode_2500(dev)) + data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | + SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; + else + data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | + SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; + + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* assert clk_req */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_PLL_CLK; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* check for clk_ack assertion */ + ret = serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_PLL_CLK, SERDES_PLL_CLK); + + if (ret) { + dev_err(dev, "Serdes PLL clk request timeout\n"); + return ret; + } + + /* assert lane reset*/ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_RST; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* check for assert lane reset reflection */ + ret = serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_RST, SERDES_RST); + + if (ret) { + dev_err(dev, "Serdes assert lane reset timeout\n"); + return ret; + } + + /* move power state to P0 */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data &= ~SERDES_PWR_ST_MASK; + data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* Check for P0 state */ + ret = serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_PWR_ST_MASK, + SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); + + if (ret) { + dev_err(dev, "Serdes power state P0 timeout.\n"); + return ret; + } + + /* PSE only - ungate SGMII PHY Rx Clock*/ + ret = mac_check_pse(dev, &is_pse); + if (ret) { + dev_err(dev, "Failed to determine MAC type.\n"); + return ret; + } + + if (is_pse) { + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_PHY_RX_CLK; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + } + + return 0; +} + +static int xpcs_access(struct udevice *dev, int reg, int v) +{ + /* + * Common read/write helper function + * + * It may seem a bit odd at a first glance that we use bus->read() + * directly insetad of one of the wrapper functions. But: + * + * (1) phy_read() can't be used because we do not access an acutal PHY, + * but a MAC-internal submodule. + * + * (2) miiphy_read() can't be used because it assumes MDIO_DEVAD_NONE. + */ + + int port = INTEL_MGBE_XPCS_ADDR; + int devad = 0x1f; + u16 val; + struct eqos_priv *eqos; + struct mii_dev *bus; + + eqos = dev_get_priv(dev); + bus = eqos->mii; + + if (v < 0) + return bus->read(bus, port, devad, reg); + + val = v; + return bus->write(bus, port, devad, reg, val); +} + +static int xpcs_read(struct udevice *dev, int reg) +{ + return xpcs_access(dev, reg, -1); +} + +static int xpcs_write(struct udevice *dev, int reg, u16 val) +{ + return xpcs_access(dev, reg, val); +} + +static int xpcs_clr_bits(struct udevice *dev, int reg, u16 bits) +{ + int ret; + + ret = xpcs_read(dev, reg); + if (ret < 0) + return ret; + + ret &= ~bits; + + return xpcs_write(dev, reg, ret); +} + +static int xpcs_set_bits(struct udevice *dev, int reg, u16 bits) +{ + int ret; + + ret = xpcs_read(dev, reg); + if (ret < 0) + return ret; + + ret |= bits; + + return xpcs_write(dev, reg, ret); +} + +static int xpcs_init(struct udevice *dev) +{ + /* Based on linux/drivers/net/pcs/pcs-xpcs.c */ + struct eqos_priv *eqos = dev_get_priv(dev); + phy_interface_t interface = eqos->config->interface(dev); + + if (interface != PHY_INTERFACE_MODE_SGMII) + return 0; + + if (xpcs_clr_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN) || + xpcs_set_bits(dev, VR_MII_AN_CTRL, XPCS_MODE_SGMII) || + xpcs_set_bits(dev, VR_MII_DIG_CTRL1, XPCS_MAC_AUTO_SW) || + xpcs_set_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN)) + return -EIO; + + return 0; +} + +static int eqos_probe_ressources_intel(struct udevice *dev) +{ + int ret; + + ret = eqos_get_base_addr_pci(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_pci failed: %d\n", ret); + return ret; + } + + limit_fifo_size(dev); + + ret = pci_config(dev); + if (ret) { + dev_err(dev, "pci_config failed: %d\n", ret); + return ret; + } + + return 0; +} + +struct eqos_config eqos_intel_config; + +/* + * overwrite __weak function from eqos_intel.c + * + * For PCI devices the devcie tree is optional. Choose driver data based on PCI + * IDs instead. + */ +void *eqos_get_driver_data(struct udevice *dev) +{ + const struct pci_device_id *id; + const struct pci_child_plat *plat; + + plat = dev_get_parent_plat(dev); + + if (!plat) + return NULL; + + /* last intel_pci_ids element is zero initialized */ + for (id = intel_pci_ids; id->vendor != 0; id++) { + if (id->vendor == plat->vendor && id->device == plat->device) + return &eqos_intel_config; + } + + return NULL; +} + +static int eqos_start_resets_intel(struct udevice *dev) +{ + int ret; + + ret = xpcs_init(dev); + if (ret) { + dev_err(dev, "xpcs init failed.\n"); + return ret; + } + + ret = serdes_powerup(dev); + if (ret) { + dev_err(dev, "Failed to power up serdes.\n"); + return ret; + } + + return 0; +} + +static ulong eqos_get_tick_clk_rate_intel(struct udevice *dev) +{ + return 0; +} + +static int eqos_get_enetaddr_intel(struct udevice *dev) +{ + /* Assume MAC address is programmed by previous boot stage */ + struct eth_pdata *plat = dev_get_plat(dev); + struct eqos_priv *eqos = dev_get_priv(dev); + u8 *lo = (u8 *)&eqos->mac_regs->address0_low; + u8 *hi = (u8 *)&eqos->mac_regs->address0_high; + + plat->enetaddr[0] = lo[0]; + plat->enetaddr[1] = lo[1]; + plat->enetaddr[2] = lo[2]; + plat->enetaddr[3] = lo[3]; + plat->enetaddr[4] = hi[0]; + plat->enetaddr[5] = hi[1]; + + return 0; +} + +static phy_interface_t eqos_get_interface_intel(const struct udevice *dev) +{ + struct pci_child_plat *plat = dev_get_parent_plat(dev); + + if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL) + return PHY_INTERFACE_MODE_NA; + + switch (plat->device) { + /* The GbE Host Controller has no RGMII interface */ + case PCI_DEVICE_ID_INTEL_EHL_RGMII1G: + return PHY_INTERFACE_MODE_NA; + + case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G: + return PHY_INTERFACE_MODE_RGMII; + + /* Host SGMII and Host SGMII2G5 share the same device id */ + case PCI_DEVICE_ID_INTEL_EHL_SGMII1: + case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5: + return PHY_INTERFACE_MODE_SGMII; + }; + + return PHY_INTERFACE_MODE_NA; +} + +static struct eqos_ops eqos_intel_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_ressources_intel, + .eqos_remove_resources = eqos_null_ops, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_intel, + .eqos_stop_clks = eqos_null_ops, + .eqos_start_clks = eqos_null_ops, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_null_ops, + .eqos_get_enetaddr = eqos_get_enetaddr_intel, + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_intel, +}; + +struct eqos_config eqos_intel_config = { + .reg_access_always_ok = false, + .mdio_wait = 10, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = eqos_get_interface_intel, + .ops = &eqos_intel_ops +}; + +extern U_BOOT_DRIVER(eth_eqos); +U_BOOT_PCI_DEVICE(eth_eqos, intel_pci_ids); diff --git a/drivers/net/dwc_eth_qos_intel.h b/drivers/net/dwc_eth_qos_intel.h new file mode 100644 index 0000000..847c75e --- /dev/null +++ b/drivers/net/dwc_eth_qos_intel.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2023-2024 DENX Software Engineering GmbH + * Philip Oberfichtner <pro@denx.de> + * + * This header is based on linux v6.6.39, + * + * drivers/net/pcs/pcs-xpcs.h + * drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h, + * + * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates + * Copyright (c) 2020 Intel Corporation + */ + +#ifndef __DWMAC_INTEL_H__ +#define __DWMAC_INTEL_H__ + +#define POLL_DELAY_US 8 + +/* SERDES Register */ +#define SERDES_GCR 0x0 /* Global Conguration */ +#define SERDES_GSR0 0x5 /* Global Status Reg0 */ +#define SERDES_GCR0 0xb /* Global Configuration Reg0 */ + +/* SERDES defines */ +#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ +#define SERDES_RST BIT(2) /* Serdes Reset */ +#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ +#define SERDES_RATE_MASK GENMASK(9, 8) +#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */ +#define SERDES_LINK_MODE_MASK GENMASK(2, 1) +#define SERDES_PWR_ST_SHIFT 4 +#define SERDES_PWR_ST_P0 0x0 +#define SERDES_PWR_ST_P3 0x3 +#define SERDES_LINK_MODE_2G5 0x3 +#define SERSED_LINK_MODE_1G 0x2 +#define SERDES_PCLK_37p5MHZ 0x0 +#define SERDES_PCLK_70MHZ 0x1 +#define SERDES_RATE_PCIE_GEN1 0x0 +#define SERDES_RATE_PCIE_GEN2 0x1 +#define SERDES_RATE_PCIE_SHIFT 8 +#define SERDES_PCLK_SHIFT 12 + +#define INTEL_MGBE_ADHOC_ADDR 0x15 +#define INTEL_MGBE_XPCS_ADDR 0x16 + +/* XPCS defines */ +#define XPCS_MODE_SGMII BIT(2) +#define XPCS_MAC_AUTO_SW BIT(9) +#define XPCS_AN_CL37_EN BIT(12) + +#define VR_MII_MMD_CTRL 0x0000 +#define VR_MII_DIG_CTRL1 0x8000 +#define VR_MII_AN_CTRL 0x8001 + +#endif /* __DWMAC_INTEL_H__ */ diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index 77d6263..de0ae09 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -522,6 +522,12 @@ static int eqos_probe_resources_qcom(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + pr_err("eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + interface = eqos->config->interface(dev); if (interface == PHY_INTERFACE_MODE_NA) { diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index c4557e5..9fc8c68 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -311,6 +311,12 @@ static int eqos_probe_resources_rk(struct udevice *dev) int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; int ret; + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + data = calloc(1, sizeof(struct rockchip_platform_data)); if (!data) return -ENOMEM; diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c index 09e714c..d9ace43 100644 --- a/drivers/net/dwc_eth_qos_starfive.c +++ b/drivers/net/dwc_eth_qos_starfive.c @@ -183,6 +183,12 @@ static int eqos_probe_resources_jh7110(struct udevice *dev) struct starfive_platform_data *data; int ret; + ret = eqos_get_base_addr_dt(dev); + if (ret) { + pr_err("eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + data = calloc(1, sizeof(struct starfive_platform_data)); if (!data) return -ENOMEM; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index cffaa10..f3a973f 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -234,6 +234,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) interface = eqos->config->interface(dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + if (interface == PHY_INTERFACE_MODE_NA) { dev_err(dev, "Invalid PHY interface\n"); return -EINVAL; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 663d900..8f432b8 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -7,10 +7,8 @@ tested on both gig copper and gig fiber boards ***************************************************************************/ /******************************************************************************* - Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. - Contact Information: Linux NICS <linux.nics@intel.com> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 @@ -107,6 +105,12 @@ static struct pci_device_id e1000_supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_K) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LMVP) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_V) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_IT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, @@ -1568,6 +1572,12 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_ICH8_IGP_M: hw->mac_type = e1000_ich8lan; break; + case PCI_DEVICE_ID_INTEL_I226_K: + case PCI_DEVICE_ID_INTEL_I226_LMVP: + case PCI_DEVICE_ID_INTEL_I226_LM: + case PCI_DEVICE_ID_INTEL_I226_V: + case PCI_DEVICE_ID_INTEL_I226_IT: + case PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I210_COPPER: @@ -1730,7 +1740,6 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); - switch (hw->mac_type) { case e1000_igb: /* IGB is cool */ return; @@ -2582,7 +2591,6 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) return ret_val; } - } else { if (hw->mac_type == e1000_ich8lan) { @@ -4842,6 +4850,8 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->phy_type = e1000_phy_igb; break; case I225_I_PHY_ID: + case I226_LM_PHY_ID: + case I226_I_PHY_ID: hw->phy_type = e1000_phy_igc; break; /* Fall Through */ @@ -4953,6 +4963,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) match = true; if (hw->phy_id == I225_I_PHY_ID) match = true; + if (hw->phy_id == I226_LM_PHY_ID) + match = true; + if (hw->phy_id == I226_I_PHY_ID) + match = true; break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); @@ -5198,7 +5212,6 @@ e1000_configure_tx(struct e1000_hw *hw) E1000_WRITE_REG(hw, TARC1, tarc); } - e1000_config_collision_dist(hw); /* Setup Transmit Descriptor Settings for eop descriptor */ hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; @@ -5209,7 +5222,6 @@ e1000_configure_tx(struct e1000_hw *hw) else hw->txd_cmd |= E1000_TXD_CMD_RS; - if (hw->mac_type == e1000_igb) { E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index e131112..5ca720f 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /******************************************************************************* - Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. Copyright 2011 Freescale Semiconductor, Inc. @@ -402,7 +401,6 @@ struct e1000_phy_stats { off */ #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ - #define NUM_DEV_IDS 16 #define NODE_ADDRESS_SIZE 6 @@ -1069,7 +1067,6 @@ typedef enum { e1000_ffe_config_blocked } e1000_ffe_config; - /* Structure containing variables used by the shared code (e1000_hw.c) */ struct e1000_hw { const char *name; @@ -2128,7 +2125,6 @@ struct e1000_hw { /* In-Band Control Register (Page 194, Register 18) */ #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ - /* Bits... * 15-5: page * 4-0: register offset @@ -2421,7 +2417,9 @@ struct e1000_hw { #define BME1000_E_PHY_ID 0x01410CB0 #define I210_I_PHY_ID 0x01410C00 +#define I226_LM_PHY_ID 0x67C9DC10 #define I225_I_PHY_ID 0x67C9DCC0 +#define I226_I_PHY_ID 0x67C9DCD0 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF diff --git a/drivers/net/essedma.c b/drivers/net/essedma.c new file mode 100644 index 0000000..fccc5f5 --- /dev/null +++ b/drivers/net/essedma.c @@ -0,0 +1,1192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + * + * Copyright (c) 2021 Toco Technologies FZE <contact@toco.ae> + * Copyright (c) 2021 Gabor Juhos <j4g8y7@gmail.com> + * + * Qualcomm ESS EDMA ethernet driver + */ + +#include <asm/io.h> +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <log.h> +#include <miiphy.h> +#include <net.h> +#include <reset.h> + +#include "essedma.h" + +#define EDMA_MAX_PKT_SIZE (PKTSIZE_ALIGN + PKTALIGN) + +#define EDMA_RXQ_ID 0 +#define EDMA_TXQ_ID 0 + +/* descriptor ring */ +struct edma_ring { + u16 count; /* number of descriptors in the ring */ + void *hw_desc; /* descriptor ring virtual address */ + unsigned int hw_size; /* hw descriptor ring length in bytes */ + dma_addr_t dma; /* descriptor ring physical address */ + u16 head; /* next Tx descriptor to fill */ + u16 tail; /* next Tx descriptor to clean */ +}; + +struct ess_switch { + phys_addr_t base; + struct phy_device *phydev[ESS_PORTS_NUM]; + u32 phy_mask; + ofnode ports_node; + phy_interface_t port_wrapper_mode; + int num_phy; +}; + +struct essedma_priv { + phys_addr_t base; + struct udevice *dev; + struct clk ess_clk; + struct reset_ctl ess_rst; + struct udevice *mdio_dev; + struct ess_switch esw; + phys_addr_t psgmii_base; + struct edma_ring tpd_ring; + struct edma_ring rfd_ring; +}; + +static void esw_port_loopback_set(struct ess_switch *esw, int port, + bool enable) +{ + u32 t; + + t = readl(esw->base + ESS_PORT_LOOKUP_CTRL(port)); + if (enable) + t |= ESS_PORT_LOOP_BACK_EN; + else + t &= ~ESS_PORT_LOOP_BACK_EN; + writel(t, esw->base + ESS_PORT_LOOKUP_CTRL(port)); +} + +static void esw_port_loopback_set_all(struct ess_switch *esw, bool enable) +{ + int i; + + for (i = 1; i < ESS_PORTS_NUM; i++) + esw_port_loopback_set(esw, i, enable); +} + +static void ess_reset(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + reset_assert(&priv->ess_rst); + mdelay(10); + + reset_deassert(&priv->ess_rst); + mdelay(10); +} + +void qca8075_ess_reset(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct phy_device *psgmii_phy; + int i, val; + + /* Find the PSGMII PHY */ + psgmii_phy = priv->esw.phydev[priv->esw.num_phy - 1]; + + /* Fix phy psgmii RX 20bit */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b); + + /* Reset phy psgmii */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x001b); + + /* Release reset phy psgmii */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b); + for (i = 0; i < 100; i++) { + val = phy_read_mmd(psgmii_phy, MDIO_MMD_PMAPMD, 0x28); + if (val & 0x1) + break; + mdelay(1); + } + if (i >= 100) + printf("QCA807x PSGMII PLL_VCO_CALIB Not Ready\n"); + + /* + * Check qca8075 psgmii calibration done end. + * Freeze phy psgmii RX CDR + */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, 0x1a, 0x2230); + + ess_reset(dev); + + /* Check ipq psgmii calibration done start */ + for (i = 0; i < 100; i++) { + val = readl(priv->psgmii_base + PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_2); + if (val & 0x1) + break; + mdelay(1); + } + if (i >= 100) + printf("PSGMII PLL_VCO_CALIB Not Ready\n"); + + /* + * Check ipq psgmii calibration done end. + * Relesae phy psgmii RX CDR + */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, 0x1a, 0x3230); + + /* Release phy psgmii RX 20bit */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005f); +} + +#define PSGMII_ST_NUM_RETRIES 20 +#define PSGMII_ST_PKT_COUNT (4 * 1024) +#define PSGMII_ST_PKT_SIZE 1504 + +/* + * Transmitting one byte over a 1000Mbps link requires 8 ns. + * Additionally, use + 1 ns for safety to compensate latencies + * and such. + */ +#define PSGMII_ST_TRAFFIC_TIMEOUT_NS \ + (PSGMII_ST_PKT_COUNT * PSGMII_ST_PKT_SIZE * (8 + 1)) + +#define PSGMII_ST_TRAFFIC_TIMEOUT \ + DIV_ROUND_UP(PSGMII_ST_TRAFFIC_TIMEOUT_NS, 1000000) + +static bool psgmii_self_test_repeat; + +static void psgmii_st_phy_power_down(struct phy_device *phydev) +{ + int val; + + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + val |= QCA807X_POWER_DOWN; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, val); +} + +static void psgmii_st_phy_prepare(struct phy_device *phydev) +{ + int val; + + /* check phydev combo port */ + val = phy_read(phydev, MDIO_DEVAD_NONE, + QCA807X_CHIP_CONFIGURATION); + if (val) { + /* Select copper page */ + val |= QCA807X_MEDIA_PAGE_SELECT; + phy_write(phydev, MDIO_DEVAD_NONE, + QCA807X_CHIP_CONFIGURATION, val); + } + + /* Force no link by power down */ + psgmii_st_phy_power_down(phydev); + + /* Packet number (Non documented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8021, PSGMII_ST_PKT_COUNT); + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8062, PSGMII_ST_PKT_SIZE); + + /* Fix MDI status */ + val = phy_read(phydev, MDIO_DEVAD_NONE, QCA807X_FUNCTION_CONTROL); + val &= ~QCA807X_MDI_CROSSOVER_MODE_MASK; + val |= FIELD_PREP(QCA807X_MDI_CROSSOVER_MODE_MASK, + QCA807X_MDI_CROSSOVER_MODE_MANUAL_MDI); + val &= ~QCA807X_POLARITY_REVERSAL; + phy_write(phydev, MDIO_DEVAD_NONE, QCA807X_FUNCTION_CONTROL, val); +} + +static void psgmii_st_phy_recover(struct phy_device *phydev) +{ + int val; + + /* Packet number (Non documented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8021, 0x0); + + /* Disable CRC checker and packet counter */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER); + val &= ~QCA807X_MMD7_PACKET_COUNTER_SELFCLR; + val &= ~QCA807X_MMD7_CRC_PACKET_COUNTER_EN; + phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER, val); + + /* Disable traffic (Undocumented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8020, 0x0); +} + +static void psgmii_st_phy_start_traffic(struct phy_device *phydev) +{ + int val; + + /* Enable CRC checker and packet counter */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER); + val |= QCA807X_MMD7_CRC_PACKET_COUNTER_EN; + phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER, val); + + /* Start traffic (Undocumented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8020, 0xa000); +} + +static bool psgmii_st_phy_check_counters(struct phy_device *phydev) +{ + u32 tx_ok; + + /* + * The number of test packets is limited to 65535 so + * only read the lower 16 bits of the counter. + */ + tx_ok = phy_read_mmd(phydev, MDIO_MMD_AN, + QCA807X_MMD7_VALID_EGRESS_COUNTER_2); + + return (tx_ok == PSGMII_ST_PKT_COUNT); +} + +static void psgmii_st_phy_reset_loopback(struct phy_device *phydev) +{ + /* reset the PHY */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, 0x9000); + + /* enable loopback mode */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, 0x4140); +} + +static inline bool psgmii_st_phy_link_is_up(struct phy_device *phydev) +{ + int val; + + val = phy_read(phydev, MDIO_DEVAD_NONE, QCA807X_PHY_SPECIFIC); + return !!(val & QCA807X_PHY_SPECIFIC_LINK); +} + +static bool psgmii_st_phy_wait(struct ess_switch *esw, u32 mask, + int retries, int delay, + bool (*check)(struct phy_device *)) +{ + int i; + + for (i = 0; i < retries; i++) { + int phy; + + for (phy = 0; phy < esw->num_phy - 1; phy++) { + u32 phybit = BIT(phy); + + if (!(mask & phybit)) + continue; + + if (check(esw->phydev[phy])) + mask &= ~phybit; + } + + if (!mask) + break; + + mdelay(delay); + } + + return (!mask); +} + +static bool psgmii_st_phy_wait_link(struct ess_switch *esw, u32 mask) +{ + return psgmii_st_phy_wait(esw, mask, 100, 10, + psgmii_st_phy_link_is_up); +} + +static bool psgmii_st_phy_wait_tx_complete(struct ess_switch *esw, u32 mask) +{ + return psgmii_st_phy_wait(esw, mask, PSGMII_ST_TRAFFIC_TIMEOUT, 1, + psgmii_st_phy_check_counters); +} + +static bool psgmii_st_run_test_serial(struct ess_switch *esw) +{ + bool result = true; + int i; + + for (i = 0; i < esw->num_phy - 1; i++) { + struct phy_device *phydev = esw->phydev[i]; + + psgmii_st_phy_reset_loopback(phydev); + + psgmii_st_phy_wait_link(esw, BIT(i)); + + psgmii_st_phy_start_traffic(phydev); + + /* wait for the traffic to complete */ + result &= psgmii_st_phy_wait_tx_complete(esw, BIT(i)); + + /* Power down */ + psgmii_st_phy_power_down(phydev); + + if (!result) + break; + } + + return result; +} + +static bool psgmii_st_run_test_parallel(struct ess_switch *esw) +{ + bool result; + int i; + + /* enable loopback mode on all PHYs */ + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_reset_loopback(esw->phydev[i]); + + psgmii_st_phy_wait_link(esw, esw->phy_mask); + + /* start traffic on all PHYs parallely */ + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_start_traffic(esw->phydev[i]); + + /* wait for the traffic to complete on all PHYs */ + result = psgmii_st_phy_wait_tx_complete(esw, esw->phy_mask); + + /* Power down all PHYs */ + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_power_down(esw->phydev[i]); + + return result; +} + +struct psgmii_st_stats { + int succeed; + int failed; + int failed_max; + int failed_cont; +}; + +static void psgmii_st_update_stats(struct psgmii_st_stats *stats, + bool success) +{ + if (success) { + stats->succeed++; + stats->failed_cont = 0; + return; + } + + stats->failed++; + stats->failed_cont++; + if (stats->failed_max < stats->failed_cont) + stats->failed_max = stats->failed_cont; +} + +static void psgmii_self_test(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct ess_switch *esw = &priv->esw; + struct psgmii_st_stats stats; + bool result = false; + unsigned long tm; + int i; + + memset(&stats, 0, sizeof(stats)); + + tm = get_timer(0); + + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_prepare(esw->phydev[i]); + + for (i = 0; i < PSGMII_ST_NUM_RETRIES; i++) { + qca8075_ess_reset(dev); + + /* enable loopback mode on the switch's ports */ + esw_port_loopback_set_all(esw, true); + + /* run test on each PHYs individually after each other */ + result = psgmii_st_run_test_serial(esw); + + if (result) { + /* run test on each PHYs parallely */ + result = psgmii_st_run_test_parallel(esw); + } + + psgmii_st_update_stats(&stats, result); + + if (psgmii_self_test_repeat) + continue; + + if (result) + break; + } + + for (i = 0; i < esw->num_phy - 1; i++) { + /* Configuration recover */ + psgmii_st_phy_recover(esw->phydev[i]); + + /* Disable loopback */ + phy_write(esw->phydev[i], MDIO_DEVAD_NONE, + QCA807X_FUNCTION_CONTROL, 0x6860); + phy_write(esw->phydev[i], MDIO_DEVAD_NONE, MII_BMCR, 0x9040); + } + + /* disable loopback mode on the switch's ports */ + esw_port_loopback_set_all(esw, false); + + tm = get_timer(tm); + dev_dbg(priv->dev, "\nPSGMII self-test: succeed %d, failed %d (max %d), duration %lu.%03lu secs\n", + stats.succeed, stats.failed, stats.failed_max, + tm / 1000, tm % 1000); +} + +static int ess_switch_disable_lookup(struct ess_switch *esw) +{ + int val; + int i; + + /* Disable port lookup for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + int ess_port_vid; + + val = readl(esw->base + ESS_PORT_LOOKUP_CTRL(i)); + val &= ~ESS_PORT_VID_MEM_MASK; + + switch (i) { + case 0: + fallthrough; + case 5: + /* CPU,WAN port -> nothing */ + ess_port_vid = 0; + break; + case 1 ... 4: + /* LAN ports -> all other LAN ports */ + ess_port_vid = GENMASK(4, 1); + ess_port_vid &= ~BIT(i); + break; + default: + return -EINVAL; + } + + val |= FIELD_PREP(ESS_PORT_VID_MEM_MASK, ess_port_vid); + + writel(val, esw->base + ESS_PORT_LOOKUP_CTRL(i)); + } + + /* Set magic value for the global forwarding register 1 */ + writel(0x3e3e3e, esw->base + ESS_GLOBAL_FW_CTRL1); + + return 0; +} + +static int ess_switch_enable_lookup(struct ess_switch *esw) +{ + int val; + int i; + + /* Enable port lookup for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + int ess_port_vid; + + val = readl(esw->base + ESS_PORT_LOOKUP_CTRL(i)); + val &= ~ESS_PORT_VID_MEM_MASK; + + switch (i) { + case 0: + /* CPU port -> all other ports */ + ess_port_vid = GENMASK(5, 1); + break; + case 1 ... 4: + /* LAN ports -> CPU and all other LAN ports */ + ess_port_vid = GENMASK(4, 0); + ess_port_vid &= ~BIT(i); + break; + case 5: + /* WAN port -> CPU port only */ + ess_port_vid = BIT(0); + break; + default: + return -EINVAL; + } + + val |= FIELD_PREP(ESS_PORT_VID_MEM_MASK, ess_port_vid); + + writel(val, esw->base + ESS_PORT_LOOKUP_CTRL(i)); + } + + /* Set magic value for the global forwarding register 1 */ + writel(0x3f3f3f, esw->base + ESS_GLOBAL_FW_CTRL1); + + return 0; +} + +static void ess_switch_init(struct ess_switch *esw) +{ + int val = 0; + int i; + + /* Set magic value for the global forwarding register 1 */ + writel(0x3e3e3e, esw->base + ESS_GLOBAL_FW_CTRL1); + + /* Set 1000M speed, full duplex and RX/TX flow control for the CPU port*/ + val &= ~ESS_PORT_SPEED_MASK; + val |= FIELD_PREP(ESS_PORT_SPEED_MASK, ESS_PORT_SPEED_1000); + val |= ESS_PORT_DUPLEX_MODE; + val |= ESS_PORT_TX_FLOW_EN; + val |= ESS_PORT_RX_FLOW_EN; + + writel(val, esw->base + ESS_PORT0_STATUS); + + /* Disable port lookup for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + val = readl(esw->base + ESS_PORT_LOOKUP_CTRL(i)); + val &= ~ESS_PORT_VID_MEM_MASK; + + writel(val, esw->base + ESS_PORT_LOOKUP_CTRL(i)); + } + + /* Set HOL settings for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + val = 0; + + val |= FIELD_PREP(EG_PORT_QUEUE_NUM_MASK, 30); + if (i == 0 || i == 5) { + val |= FIELD_PREP(EG_PRI5_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI4_QUEUE_NUM_MASK, 4); + } + val |= FIELD_PREP(EG_PRI3_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI2_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI1_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI0_QUEUE_NUM_MASK, 4); + + writel(val, esw->base + ESS_PORT_HOL_CTRL0(i)); + + val = readl(esw->base + ESS_PORT_HOL_CTRL1(i)); + val &= ~ESS_ING_BUF_NUM_0_MASK; + val |= FIELD_PREP(ESS_ING_BUF_NUM_0_MASK, 6); + + writel(val, esw->base + ESS_PORT_HOL_CTRL1(i)); + } + + /* Give switch some time */ + mdelay(1); + + /* Enable RX and TX MAC-s */ + val = readl(esw->base + ESS_PORT0_STATUS); + val |= ESS_PORT_TXMAC_EN; + val |= ESS_PORT_RXMAC_EN; + + writel(val, esw->base + ESS_PORT0_STATUS); + + /* Set magic value for the global forwarding register 1 */ + writel(0x7f7f7f, esw->base + ESS_GLOBAL_FW_CTRL1); +} + +static int essedma_of_phy(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct ess_switch *esw = &priv->esw; + int num_phy = 0, ret = 0; + ofnode node; + int i; + + ofnode_for_each_subnode(node, esw->ports_node) { + struct ofnode_phandle_args phandle_args; + struct phy_device *phydev; + u32 phy_addr; + + if (ofnode_is_enabled(node)) { + if (ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, + &phandle_args)) { + dev_dbg(priv->dev, "Failed to find phy-handle\n"); + return -ENODEV; + } + + ret = ofnode_read_u32(phandle_args.node, "reg", &phy_addr); + if (ret) { + dev_dbg(priv->dev, "Missing reg property in PHY node %s\n", + ofnode_get_name(phandle_args.node)); + return ret; + } + + phydev = dm_mdio_phy_connect(priv->mdio_dev, phy_addr, + dev, priv->esw.port_wrapper_mode); + if (!phydev) { + dev_dbg(priv->dev, "Failed to find phy on addr %d\n", phy_addr); + return -ENODEV; + } + + phydev->node = phandle_args.node; + ret = phy_config(phydev); + + esw->phydev[num_phy] = phydev; + + num_phy++; + } + } + + esw->num_phy = num_phy; + + for (i = 0; i < esw->num_phy - 1; i++) + esw->phy_mask |= BIT(i); + + return ret; +} + +static int essedma_of_switch(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + int port_wrapper_mode = -1; + + priv->esw.ports_node = ofnode_find_subnode(dev_ofnode(dev), "ports"); + if (!ofnode_valid(priv->esw.ports_node)) { + printf("Failed to find ports node\n"); + return -EINVAL; + } + + port_wrapper_mode = ofnode_read_phy_mode(priv->esw.ports_node); + if (port_wrapper_mode == -1) + return -EINVAL; + + priv->esw.port_wrapper_mode = port_wrapper_mode; + + return essedma_of_phy(dev); +} + +static void ipq40xx_edma_start_rx_tx(struct essedma_priv *priv) +{ + volatile u32 data; + + /* enable RX queues */ + data = readl(priv->base + EDMA_REG_RXQ_CTRL); + data |= EDMA_RXQ_CTRL_EN; + writel(data, priv->base + EDMA_REG_RXQ_CTRL); + + /* enable TX queues */ + data = readl(priv->base + EDMA_REG_TXQ_CTRL); + data |= EDMA_TXQ_CTRL_TXQ_EN; + writel(data, priv->base + EDMA_REG_TXQ_CTRL); +} + +/* + * ipq40xx_edma_init_desc() + * Update descriptor ring size, + * Update buffer and producer/consumer index + */ +static void ipq40xx_edma_init_desc(struct essedma_priv *priv) +{ + struct edma_ring *rfd_ring; + struct edma_ring *etdr; + volatile u32 data = 0; + u16 hw_cons_idx = 0; + + /* Set the base address of every TPD ring. */ + etdr = &priv->tpd_ring; + + /* Update TX descriptor ring base address. */ + writel((u32)(etdr->dma & 0xffffffff), + priv->base + EDMA_REG_TPD_BASE_ADDR_Q(EDMA_TXQ_ID)); + data = readl(priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + + /* Calculate hardware consumer index for Tx. */ + hw_cons_idx = FIELD_GET(EDMA_TPD_CONS_IDX_MASK, data); + etdr->head = hw_cons_idx; + etdr->tail = hw_cons_idx; + data &= ~EDMA_TPD_PROD_IDX_MASK; + data |= hw_cons_idx; + + /* Update producer index for Tx. */ + writel(data, priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + + /* Update SW consumer index register for Tx. */ + writel(hw_cons_idx, + priv->base + EDMA_REG_TX_SW_CONS_IDX_Q(EDMA_TXQ_ID)); + + /* Set TPD ring size. */ + writel((u32)(etdr->count & EDMA_TPD_RING_SIZE_MASK), + priv->base + EDMA_REG_TPD_RING_SIZE); + + /* Configure Rx ring. */ + rfd_ring = &priv->rfd_ring; + + /* Update Receive Free descriptor ring base address. */ + writel((u32)(rfd_ring->dma & 0xffffffff), + priv->base + EDMA_REG_RFD_BASE_ADDR_Q(EDMA_RXQ_ID)); + data = readl(priv->base + EDMA_REG_RFD_BASE_ADDR_Q(EDMA_RXQ_ID)); + + /* Update RFD ring size and RX buffer size. */ + data = (rfd_ring->count & EDMA_RFD_RING_SIZE_MASK) + << EDMA_RFD_RING_SIZE_SHIFT; + data |= (EDMA_MAX_PKT_SIZE & EDMA_RX_BUF_SIZE_MASK) + << EDMA_RX_BUF_SIZE_SHIFT; + writel(data, priv->base + EDMA_REG_RX_DESC0); + + /* Disable TX FIFO low watermark and high watermark */ + writel(0, priv->base + EDMA_REG_TXF_WATER_MARK); + + /* Load all of base address above */ + data = readl(priv->base + EDMA_REG_TX_SRAM_PART); + data |= 1 << EDMA_LOAD_PTR_SHIFT; + writel(data, priv->base + EDMA_REG_TX_SRAM_PART); +} + +static void ipq40xx_edma_init_rfd_ring(struct essedma_priv *priv) +{ + struct edma_ring *erdr = &priv->rfd_ring; + struct edma_rfd *rfds = erdr->hw_desc; + int i; + + for (i = 0; i < erdr->count; i++) + rfds[i].buffer_addr = virt_to_phys(net_rx_packets[i]); + + flush_dcache_range(erdr->dma, erdr->dma + erdr->hw_size); + + /* setup producer index */ + erdr->head = erdr->count - 1; + writel(erdr->head, priv->base + EDMA_REG_RFD_IDX_Q(EDMA_RXQ_ID)); +} + +static void ipq40xx_edma_configure(struct essedma_priv *priv) +{ + u32 tmp; + int i; + + /* Set RSS type */ + writel(IPQ40XX_EDMA_RSS_TYPE_NONE, priv->base + EDMA_REG_RSS_TYPE); + + /* Configure RSS indirection table. + * 128 hash will be configured in the following + * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively + * and so on + */ + for (i = 0; i < EDMA_NUM_IDT; i++) + writel(EDMA_RSS_IDT_VALUE, priv->base + EDMA_REG_RSS_IDT(i)); + + /* Set RFD burst number */ + tmp = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT); + + /* Set RFD prefetch threshold */ + tmp |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT); + + /* Set RFD in host ring low threshold to generte interrupt */ + tmp |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT); + writel(tmp, priv->base + EDMA_REG_RX_DESC1); + + /* configure reception control data. */ + + /* Set Rx FIFO threshold to start to DMA data to host */ + tmp = EDMA_FIFO_THRESH_128_BYTE; + + /* Set RX remove vlan bit */ + tmp |= EDMA_RXQ_CTRL_RMV_VLAN; + writel(tmp, priv->base + EDMA_REG_RXQ_CTRL); + + /* Configure transmission control data */ + tmp = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT); + tmp |= EDMA_TXQ_CTRL_TPD_BURST_EN; + tmp |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT); + writel(tmp, priv->base + EDMA_REG_TXQ_CTRL); +} + +static void ipq40xx_edma_stop_rx_tx(struct essedma_priv *priv) +{ + volatile u32 data; + + data = readl(priv->base + EDMA_REG_RXQ_CTRL); + data &= ~EDMA_RXQ_CTRL_EN; + writel(data, priv->base + EDMA_REG_RXQ_CTRL); + data = readl(priv->base + EDMA_REG_TXQ_CTRL); + data &= ~EDMA_TXQ_CTRL_TXQ_EN; + writel(data, priv->base + EDMA_REG_TXQ_CTRL); +} + +static int ipq40xx_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct edma_ring *erdr = &priv->rfd_ring; + struct edma_rrd *rrd; + u32 hw_tail; + u8 *rx_pkt; + + hw_tail = readl(priv->base + EDMA_REG_RFD_IDX_Q(EDMA_RXQ_ID)); + hw_tail = FIELD_GET(EDMA_RFD_CONS_IDX_MASK, hw_tail); + + if (hw_tail == erdr->tail) + return -EAGAIN; + + rx_pkt = net_rx_packets[erdr->tail]; + invalidate_dcache_range((unsigned long)rx_pkt, + (unsigned long)(rx_pkt + EDMA_MAX_PKT_SIZE)); + + rrd = (struct edma_rrd *)rx_pkt; + + /* Check if RRD is valid */ + if (!(rrd->rrd7 & EDMA_RRD7_DESC_VALID)) + return 0; + + *packetp = rx_pkt + EDMA_RRD_SIZE; + + /* get the packet size */ + return rrd->rrd6; +} + +static int ipq40xx_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct edma_ring *erdr; + + erdr = &priv->rfd_ring; + + /* Update the producer index */ + writel(erdr->head, priv->base + EDMA_REG_RFD_IDX_Q(EDMA_RXQ_ID)); + + erdr->head++; + if (erdr->head == erdr->count) + erdr->head = 0; + + /* Update the consumer index */ + erdr->tail++; + if (erdr->tail == erdr->count) + erdr->tail = 0; + + writel(erdr->tail, + priv->base + EDMA_REG_RX_SW_CONS_IDX_Q(EDMA_RXQ_ID)); + + return 0; +} + +static int ipq40xx_eth_start(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + ipq40xx_edma_init_rfd_ring(priv); + + ipq40xx_edma_start_rx_tx(priv); + ess_switch_enable_lookup(&priv->esw); + + return 0; +} + +/* + * One TPD would be enough for sending a packet, however because the + * minimal cache line size is larger than the size of a TPD it is not + * possible to flush only one at once. To overcome this limitation + * multiple TPDs are used for sending a single packet. + */ +#define EDMA_TPDS_PER_PACKET 4 +#define EDMA_TPD_MIN_BYTES 4 +#define EDMA_MIN_PKT_SIZE (EDMA_TPDS_PER_PACKET * EDMA_TPD_MIN_BYTES) + +#define EDMA_TX_COMPLETE_TIMEOUT 1000000 + +static int ipq40xx_eth_send(struct udevice *dev, void *packet, int length) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct edma_tpd *first_tpd; + struct edma_tpd *tpds; + int i; + + if (length < EDMA_MIN_PKT_SIZE) + return 0; + + flush_dcache_range((unsigned long)(packet), + (unsigned long)(packet) + + roundup(length, ARCH_DMA_MINALIGN)); + + tpds = priv->tpd_ring.hw_desc; + for (i = 0; i < EDMA_TPDS_PER_PACKET; i++) { + struct edma_tpd *tpd; + void *frag; + + frag = packet + (i * EDMA_TPD_MIN_BYTES); + + /* get the next TPD */ + tpd = &tpds[priv->tpd_ring.head]; + if (i == 0) + first_tpd = tpd; + + /* update the software index */ + priv->tpd_ring.head++; + if (priv->tpd_ring.head == priv->tpd_ring.count) + priv->tpd_ring.head = 0; + + tpd->svlan_tag = 0; + tpd->addr = virt_to_phys(frag); + tpd->word3 = EDMA_PORT_ENABLE_ALL << EDMA_TPD_PORT_BITMAP_SHIFT; + + if (i < (EDMA_TPDS_PER_PACKET - 1)) { + tpd->len = EDMA_TPD_MIN_BYTES; + tpd->word1 = 0; + } else { + tpd->len = length; + tpd->word1 = 1 << EDMA_TPD_EOP_SHIFT; + } + + length -= EDMA_TPD_MIN_BYTES; + } + + /* make sure that memory writing completes */ + wmb(); + + flush_dcache_range((unsigned long)first_tpd, + (unsigned long)first_tpd + + EDMA_TPDS_PER_PACKET * sizeof(struct edma_tpd)); + + /* update the TX producer index */ + writel(priv->tpd_ring.head, + priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + + /* Wait for TX DMA completion */ + for (i = 0; i < EDMA_TX_COMPLETE_TIMEOUT; i++) { + u32 r, prod, cons; + + r = readl(priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + prod = FIELD_GET(EDMA_TPD_PROD_IDX_MASK, r); + cons = FIELD_GET(EDMA_TPD_CONS_IDX_MASK, r); + + if (cons == prod) + break; + + udelay(1); + } + + if (i == EDMA_TX_COMPLETE_TIMEOUT) + printf("TX timeout: packet not sent!\n"); + + /* update the software TX consumer index register */ + writel(priv->tpd_ring.head, + priv->base + EDMA_REG_TX_SW_CONS_IDX_Q(EDMA_TXQ_ID)); + + return 0; +} + +static void ipq40xx_eth_stop(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + ess_switch_disable_lookup(&priv->esw); + ipq40xx_edma_stop_rx_tx(priv); +} + +static void ipq40xx_edma_free_ring(struct edma_ring *ring) +{ + free(ring->hw_desc); +} + +/* + * Free Tx and Rx rings + */ +static void ipq40xx_edma_free_rings(struct essedma_priv *priv) +{ + ipq40xx_edma_free_ring(&priv->tpd_ring); + ipq40xx_edma_free_ring(&priv->rfd_ring); +} + +/* + * ipq40xx_edma_alloc_ring() + * allocate edma ring descriptor. + */ +static int ipq40xx_edma_alloc_ring(struct edma_ring *erd, + unsigned int desc_size) +{ + erd->head = 0; + erd->tail = 0; + + /* Alloc HW descriptors */ + erd->hw_size = roundup(desc_size * erd->count, + ARCH_DMA_MINALIGN); + + erd->hw_desc = memalign(CONFIG_SYS_CACHELINE_SIZE, erd->hw_size); + if (!erd->hw_desc) + return -ENOMEM; + + memset(erd->hw_desc, 0, erd->hw_size); + erd->dma = virt_to_phys(erd->hw_desc); + + return 0; + +} + +/* + * ipq40xx_allocate_tx_rx_rings() + */ +static int ipq40xx_edma_alloc_tx_rx_rings(struct essedma_priv *priv) +{ + int ret; + + ret = ipq40xx_edma_alloc_ring(&priv->tpd_ring, + sizeof(struct edma_tpd)); + if (ret) + return ret; + + ret = ipq40xx_edma_alloc_ring(&priv->rfd_ring, + sizeof(struct edma_rfd)); + if (ret) + goto err_free_tpd; + + return 0; + +err_free_tpd: + ipq40xx_edma_free_ring(&priv->tpd_ring); + return ret; +} + +static int ipq40xx_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct essedma_priv *priv = dev_get_priv(dev); + unsigned char *mac = pdata->enetaddr; + u32 mac_lo, mac_hi; + + mac_hi = ((u32)mac[0]) << 8 | (u32)mac[1]; + mac_lo = ((u32)mac[2]) << 24 | ((u32)mac[3]) << 16 | + ((u32)mac[4]) << 8 | (u32)mac[5]; + + writel(mac_lo, priv->base + REG_MAC_CTRL0); + writel(mac_hi, priv->base + REG_MAC_CTRL1); + + return 0; +} + +static int edma_init(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + int ret; + + priv->tpd_ring.count = IPQ40XX_EDMA_TX_RING_SIZE; + priv->rfd_ring.count = PKTBUFSRX; + + ret = ipq40xx_edma_alloc_tx_rx_rings(priv); + if (ret) + return -ENOMEM; + + ipq40xx_edma_stop_rx_tx(priv); + + /* Configure EDMA. */ + ipq40xx_edma_configure(priv); + + /* Configure descriptor Ring */ + ipq40xx_edma_init_desc(priv); + + ess_switch_disable_lookup(&priv->esw); + + return 0; +} + +static int essedma_probe(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + int ret; + + priv->dev = dev; + + priv->base = dev_read_addr_name(dev, "edma"); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->psgmii_base = dev_read_addr_name(dev, "psgmii_phy"); + if (priv->psgmii_base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->esw.base = dev_read_addr_name(dev, "base"); + if (priv->esw.base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = clk_get_by_name(dev, "ess", &priv->ess_clk); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "ess", &priv->ess_rst); + if (ret) + return ret; + + ret = clk_enable(&priv->ess_clk); + if (ret) + return ret; + + ess_reset(dev); + + ret = uclass_get_device_by_driver(UCLASS_MDIO, + DM_DRIVER_GET(ipq4019_mdio), + &priv->mdio_dev); + if (ret) { + dev_dbg(dev, "Cant find IPQ4019 MDIO: %d\n", ret); + goto err; + } + + /* OF switch and PHY parsing and configuration */ + ret = essedma_of_switch(dev); + if (ret) + goto err; + + switch (priv->esw.port_wrapper_mode) { + case PHY_INTERFACE_MODE_PSGMII: + writel(PSGMIIPHY_PLL_VCO_VAL, + priv->psgmii_base + PSGMIIPHY_PLL_VCO_RELATED_CTRL); + writel(PSGMIIPHY_VCO_VAL, priv->psgmii_base + + PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_1); + /* wait for 10ms */ + mdelay(10); + writel(PSGMIIPHY_VCO_RST_VAL, priv->psgmii_base + + PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_1); + break; + case PHY_INTERFACE_MODE_RGMII: + writel(0x1, RGMII_TCSR_ESS_CFG); + writel(0x400, priv->esw.base + ESS_RGMII_CTRL); + break; + default: + printf("Unknown MII interface\n"); + } + + if (priv->esw.port_wrapper_mode == PHY_INTERFACE_MODE_PSGMII) + psgmii_self_test(dev); + + ess_switch_init(&priv->esw); + + ret = edma_init(dev); + if (ret) + goto err; + + return 0; + +err: + reset_assert(&priv->ess_rst); + clk_disable(&priv->ess_clk); + return ret; +} + +static int essedma_remove(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + ipq40xx_edma_free_rings(priv); + + clk_disable(&priv->ess_clk); + reset_assert(&priv->ess_rst); + + return 0; +} + +static const struct eth_ops essedma_eth_ops = { + .start = ipq40xx_eth_start, + .send = ipq40xx_eth_send, + .recv = ipq40xx_eth_recv, + .free_pkt = ipq40xx_eth_free_pkt, + .stop = ipq40xx_eth_stop, + .write_hwaddr = ipq40xx_eth_write_hwaddr, +}; + +static const struct udevice_id essedma_ids[] = { + { .compatible = "qcom,ipq4019-ess", }, + { } +}; + +U_BOOT_DRIVER(essedma) = { + .name = "essedma", + .id = UCLASS_ETH, + .of_match = essedma_ids, + .probe = essedma_probe, + .remove = essedma_remove, + .priv_auto = sizeof(struct essedma_priv), + .plat_auto = sizeof(struct eth_pdata), + .ops = &essedma_eth_ops, + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/essedma.h b/drivers/net/essedma.h new file mode 100644 index 0000000..067cb44 --- /dev/null +++ b/drivers/net/essedma.h @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + * + * Copyright (c) 2021 Toco Technologies FZE <contact@toco.ae> + * Copyright (c) 2021 Gabor Juhos <j4g8y7@gmail.com> + * + * Qualcomm ESS EDMA ethernet driver + */ + +#ifndef _ESSEDMA_ETH_H +#define _ESSEDMA_ETH_H + +#define ESS_PORTS_NUM 6 + +#define ESS_RGMII_CTRL 0x4 + +#define ESS_GLOBAL_FW_CTRL1 0x624 + +#define ESS_PORT0_STATUS 0x7c +#define ESS_PORT_SPEED_MASK GENMASK(1, 0) +#define ESS_PORT_SPEED_1000 3 +#define ESS_PORT_SPEED_100 2 +#define ESS_PORT_SPEED_10 1 +#define ESS_PORT_TXMAC_EN BIT(2) +#define ESS_PORT_RXMAC_EN BIT(3) +#define ESS_PORT_TX_FLOW_EN BIT(4) +#define ESS_PORT_RX_FLOW_EN BIT(5) +#define ESS_PORT_DUPLEX_MODE BIT(6) + +#define ESS_PORT_LOOKUP_CTRL(_p) (0x660 + (_p) * 12) +#define ESS_PORT_LOOP_BACK_EN BIT(21) +#define ESS_PORT_VID_MEM_MASK GENMASK(6, 0) + +#define ESS_PORT_HOL_CTRL0(_p) (0x970 + (_p) * 8) +#define EG_PORT_QUEUE_NUM_MASK GENMASK(29, 24) + +/* Ports 0 and 5 have queues 0-5 + * Ports 1 to 4 have queues 0-3 + */ +#define EG_PRI5_QUEUE_NUM_MASK GENMASK(23, 20) +#define EG_PRI4_QUEUE_NUM_MASK GENMASK(19, 16) +#define EG_PRI3_QUEUE_NUM_MASK GENMASK(15, 12) +#define EG_PRI2_QUEUE_NUM_MASK GENMASK(11, 8) +#define EG_PRI1_QUEUE_NUM_MASK GENMASK(7, 4) +#define EG_PRI0_QUEUE_NUM_MASK GENMASK(3, 0) + +#define ESS_PORT_HOL_CTRL1(_p) (0x974 + (_p) * 8) +#define ESS_ING_BUF_NUM_0_MASK GENMASK(3, 0) + +/* QCA807x PHY registers */ +#define QCA807X_CHIP_CONFIGURATION 0x1f +#define QCA807X_MEDIA_PAGE_SELECT BIT(15) + +#define QCA807X_POWER_DOWN BIT(11) + +#define QCA807X_FUNCTION_CONTROL 0x10 +#define QCA807X_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5) +#define QCA807X_MDI_CROSSOVER_MODE_MANUAL_MDI 0 +#define QCA807X_POLARITY_REVERSAL BIT(1) + +#define QCA807X_PHY_SPECIFIC 0x11 +#define QCA807X_PHY_SPECIFIC_LINK BIT(10) + +#define QCA807X_MMD7_CRC_PACKET_COUNTER 0x8029 +#define QCA807X_MMD7_PACKET_COUNTER_SELFCLR BIT(1) +#define QCA807X_MMD7_CRC_PACKET_COUNTER_EN BIT(0) +#define QCA807X_MMD7_VALID_EGRESS_COUNTER_2 0x802e + +/* PSGMII specific registers */ +#define PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_1 0x9c +#define PSGMIIPHY_VCO_VAL 0x4ada +#define PSGMIIPHY_VCO_RST_VAL 0xada +#define PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_2 0xa0 + +#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x78c +#define PSGMIIPHY_PLL_VCO_VAL 0x2803 + +#define RGMII_TCSR_ESS_CFG 0x01953000 + +/* EDMA registers */ +#define IPQ40XX_EDMA_TX_RING_SIZE 8 +#define IPQ40XX_EDMA_RSS_TYPE_NONE 0x1 + +#define EDMA_RSS_TYPE 0 +#define EDMA_TPD_EOP_SHIFT 31 + +/* tpd word 3 bit 18-28 */ +#define EDMA_TPD_PORT_BITMAP_SHIFT 18 + +/* Enable Tx for all ports */ +#define EDMA_PORT_ENABLE_ALL 0x3E + +/* Edma receive consumer index */ +/* x = queue id */ +#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) +/* Edma transmit consumer index */ +#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) +/* TPD Index Register */ +#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) +/* Tx Descriptor Control Register */ +#define EDMA_REG_TPD_RING_SIZE 0x41C +#define EDMA_TPD_RING_SIZE_MASK 0xFFFF + +/* Transmit descriptor base address */ + /* x = queue id */ +#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) +#define EDMA_TPD_PROD_IDX_MASK GENMASK(15, 0) +#define EDMA_TPD_CONS_IDX_MASK GENMASK(31, 16) + +#define EDMA_REG_TX_SRAM_PART 0x400 +#define EDMA_LOAD_PTR_SHIFT 16 + +/* TXQ Control Register */ +#define EDMA_REG_TXQ_CTRL 0x404 +#define EDMA_TXQ_CTRL_TXQ_EN 0x20 +#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100 +#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0 +#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16 +#define EDMA_TXF_BURST 0x100 +#define EDMA_TPD_BURST 5 + +#define EDMA_REG_TXF_WATER_MARK 0x408 + +/* RSS Indirection Register */ +/* x = No. of indirection table */ +#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) +#define EDMA_NUM_IDT 16 +#define EDMA_RSS_IDT_VALUE 0x64206420 + +/* RSS Hash Function Type Register */ +#define EDMA_REG_RSS_TYPE 0x894 + +/* x = queue id */ +#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) +/* RFD Index Register */ +#define EDMA_RFD_BURST 8 +#define EDMA_RFD_THR 16 +#define EDMA_RFD_LTHR 0 +#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) + +#define EDMA_RFD_CONS_IDX_MASK GENMASK(27, 16) + +/* Rx Descriptor Control Register */ +#define EDMA_REG_RX_DESC0 0xA10 +#define EDMA_RFD_RING_SIZE_MASK 0xFFF +#define EDMA_RX_BUF_SIZE_MASK 0xFFFF +#define EDMA_RFD_RING_SIZE_SHIFT 0 +#define EDMA_RX_BUF_SIZE_SHIFT 16 + +#define EDMA_REG_RX_DESC1 0xA14 +#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0 +#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8 +#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16 + +/* RXQ Control Register */ +#define EDMA_REG_RXQ_CTRL 0xA18 +#define EDMA_FIFO_THRESH_128_BYTE 0x0 +#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002 +#define EDMA_RXQ_CTRL_EN 0x0000FF00 + +/* MAC Control Register */ +#define REG_MAC_CTRL0 0xC20 +#define REG_MAC_CTRL1 0xC24 + +/* Transmit Packet Descriptor */ +struct edma_tpd { + u16 len; /* full packet including CRC */ + u16 svlan_tag; /* vlan tag */ + u32 word1; /* byte 4-7 */ + u32 addr; /* address of buffer */ + u32 word3; /* byte 12 */ +}; + +/* Receive Return Descriptor */ +struct edma_rrd { + u16 rrd0; + u16 rrd1; + u16 rrd2; + u16 rrd3; + u16 rrd4; + u16 rrd5; + u16 rrd6; + u16 rrd7; +} __packed; + +#define EDMA_RRD_SIZE sizeof(struct edma_rrd) + +#define EDMA_RRD7_DESC_VALID BIT(15) + +/* Receive Free Descriptor */ +struct edma_rfd { + u32 buffer_addr; /* buffer address */ +}; + +#endif /* _ESSEDMA_ETH_H */ diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0a0d92b..d6d5cb5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -615,8 +615,7 @@ static int fecmxc_init(struct udevice *dev) if (fec->xcv_type != SEVENWIRE) miiphy_restart_aneg(dev); #endif - fec_open(dev); - return 0; + return fec_open(dev); } /** @@ -818,6 +817,9 @@ static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) return -ENOMEM; } + if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN)) + return 0; + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); @@ -1210,10 +1212,13 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) else if (interface == PHY_INTERFACE_MODE_RGMII || interface == PHY_INTERFACE_MODE_RGMII_ID || interface == PHY_INTERFACE_MODE_RGMII_RXID || - interface == PHY_INTERFACE_MODE_RGMII_TXID) + interface == PHY_INTERFACE_MODE_RGMII_TXID) { freq = 125000000; - else + if (is_imx93()) + freq = freq << 1; + } else { return -EINVAL; + } ret = clk_set_rate(clk_ref, freq); if (ret < 0) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 19f3f0f..63fe4b2 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -26,7 +26,8 @@ #include "fm.h" -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) +#if ((defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_BITBANGMII)) #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \ TBIANA_FULL_DUPLEX) @@ -701,8 +702,11 @@ static int init_phy(struct fm_eth *fm_eth) supported |= SUPPORTED_2500baseX_Full; #endif +#if (CONFIG_IS_ENABLED(MII) || CONFIG_IS_ENABLED(CMD_MII)) && \ + !CONFIG_IS_ENABLED(BITBANGMII) if (fm_eth->type == FM_ETH_1G_E) dtsec_init_phy(fm_eth); +#endif #ifdef CONFIG_PHYLIB #ifdef CONFIG_DM_MDIO diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 44ce000..f4e82b0 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -218,7 +218,6 @@ void qbman_eq_desc_set_response(struct qbman_eq_desc *d, qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); } - void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, uint32_t qd_bin, uint32_t qd_prio) { @@ -365,7 +364,6 @@ static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8); #define QBMAN_DQRR_RESPONSE_BPSCN 0x29 #define QBMAN_DQRR_RESPONSE_CSCN_WQ 0x2a - /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry * only once, so repeated calls can return a sequence of DQRR entries, without * requiring they be consumed immediately or in any particular order. */ diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.h b/drivers/net/fsl-mc/dpio/qbman_portal.h index 8cbc771..67ed90c 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.h +++ b/drivers/net/fsl-mc/dpio/qbman_portal.h @@ -16,7 +16,6 @@ #define QBMAN_VER_4_0_DQRR_SIZE 4 #define QBMAN_VER_4_1_DQRR_SIZE 8 - /* --------------------- */ /* portal data structure */ /* --------------------- */ @@ -130,7 +129,6 @@ static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code, return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); } - /* encode a field to a cacheline */ static inline void qb_attr_code_encode(const struct qb_attr_code *code, uint32_t *cacheline, uint32_t val) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 8781e50..f5ea2e7 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -26,6 +26,7 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/printk.h> +#include <linux/bitfield.h> #include "ftgmac100.h" @@ -57,6 +58,15 @@ enum ftgmac100_model { FTGMAC100_MODEL_FARADAY, FTGMAC100_MODEL_ASPEED, + FTGMAC100_MODEL_ASPEED_AST2700, +}; + +union ftgmac100_dma_addr { + dma_addr_t addr; + struct { + u32 lo; + u32 hi; + }; }; /** @@ -96,6 +106,8 @@ struct ftgmac100_data { /* End of RX/TX ring buffer bits. Depend on model */ u32 rxdes0_edorr_mask; u32 txdes0_edotr_mask; + + bool is_ast2700; }; /* @@ -222,7 +234,7 @@ static int ftgmac100_phy_init(struct udevice *dev) struct phy_device *phydev; int ret; - if (IS_ENABLED(CONFIG_DM_MDIO)) + if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) phydev = dm_eth_phy_connect(dev); else phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); @@ -320,8 +332,9 @@ static int ftgmac100_start(struct udevice *dev) struct eth_pdata *plat = dev_get_plat(dev); struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; + union ftgmac100_dma_addr dma_addr = {.hi = 0, .lo = 0}; struct phy_device *phydev = priv->phydev; - unsigned int maccr; + unsigned int maccr, dblac, desc_size; ulong start, end; int ret; int i; @@ -341,6 +354,7 @@ static int ftgmac100_start(struct udevice *dev) priv->rx_index = 0; for (i = 0; i < PKTBUFSTX; i++) { + priv->txdes[i].txdes2 = 0; priv->txdes[i].txdes3 = 0; priv->txdes[i].txdes0 = 0; } @@ -351,7 +365,14 @@ static int ftgmac100_start(struct udevice *dev) flush_dcache_range(start, end); for (i = 0; i < PKTBUFSRX; i++) { - priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; + unsigned int ip_align = 0; + + dma_addr.addr = (dma_addr_t)net_rx_packets[i]; + priv->rxdes[i].rxdes2 = FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, dma_addr.hi); + /* For IP alignment */ + if ((dma_addr.lo & (PKTALIGN - 1)) == 0) + ip_align = 2; + priv->rxdes[i].rxdes3 = dma_addr.lo + ip_align; priv->rxdes[i].rxdes0 = 0; } priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; @@ -361,10 +382,25 @@ static int ftgmac100_start(struct udevice *dev) flush_dcache_range(start, end); /* transmit ring */ - writel((u32)priv->txdes, &ftgmac100->txr_badr); + dma_addr.addr = (dma_addr_t)priv->txdes; + writel(dma_addr.lo, &ftgmac100->txr_badr); + writel(dma_addr.hi, &ftgmac100->txr_badr_hi); /* receive ring */ - writel((u32)priv->rxdes, &ftgmac100->rxr_badr); + dma_addr.addr = (dma_addr_t)priv->rxdes; + writel(dma_addr.lo, &ftgmac100->rxr_badr); + writel(dma_addr.hi, &ftgmac100->rxr_badr_hi); + + /* Configure TX/RX decsriptor size + * This size is calculated based on cache line. + */ + desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT; + /* The descriptor size is at least 2 descriptor units. */ + if (desc_size < 2) + desc_size = 2; + dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12); + dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size); + writel(dblac, &ftgmac100->dblac); /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); @@ -382,6 +418,10 @@ static int ftgmac100_start(struct udevice *dev) FTGMAC100_MACCR_RX_RUNT | FTGMAC100_MACCR_RX_BROADPKT; + if (priv->is_ast2700 && (priv->phydev->interface == PHY_INTERFACE_MODE_RMII || + priv->phydev->interface == PHY_INTERFACE_MODE_NCSI)) + maccr |= FTGMAC100_MACCR_RMII_ENABLE; + writel(maccr, &ftgmac100->maccr); ret = phy_startup(phydev); @@ -410,6 +450,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + /* + * Make sure there are no stale data in write-back over this area, which + * might get written into the memory while the ftgmac100 also writes + * into the same memory area. + */ + flush_dcache_range((ulong)net_rx_packets[priv->rx_index], + (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN); + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; flush_dcache_range(des_start, des_end); @@ -431,9 +479,11 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); - ulong data_start = curr_des->rxdes3; + union ftgmac100_dma_addr data_start = { .lo = 0, .hi = 0 }; ulong data_end; + data_start.hi = FIELD_GET(FTGMAC100_RXDES2_RXBUF_BADR_HI, curr_des->rxdes2); + data_start.lo = curr_des->rxdes3; invalidate_dcache_range(des_start, des_end); if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) @@ -453,9 +503,9 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) __func__, priv->rx_index, rxlen); /* Invalidate received data */ - data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); - invalidate_dcache_range(data_start, data_end); - *packetp = (uchar *)data_start; + data_end = data_start.addr + roundup(rxlen, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start.addr, data_end); + *packetp = (uchar *)data_start.addr; return rxlen; } @@ -481,6 +531,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + union ftgmac100_dma_addr dma_addr; ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); @@ -499,10 +550,12 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) length = (length < ETH_ZLEN) ? ETH_ZLEN : length; - curr_des->txdes3 = (unsigned int)packet; + dma_addr.addr = (dma_addr_t)packet; + curr_des->txdes2 = FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, dma_addr.hi); + curr_des->txdes3 = dma_addr.lo; /* Flush data to be sent */ - data_start = curr_des->txdes3; + data_start = (ulong)dma_addr.addr; data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); flush_dcache_range(data_start, data_end); @@ -565,6 +618,11 @@ static int ftgmac100_of_to_plat(struct udevice *dev) if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); + priv->is_ast2700 = false; + } else if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED_AST2700) { + priv->rxdes0_edorr_mask = BIT(30); + priv->txdes0_edotr_mask = BIT(30); + priv->is_ast2700 = true; } else { priv->rxdes0_edorr_mask = BIT(15); priv->txdes0_edotr_mask = BIT(15); @@ -655,10 +713,11 @@ static const struct eth_ops ftgmac100_ops = { }; static const struct udevice_id ftgmac100_ids[] = { - { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, - { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, - { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, - { } + { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, + { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, + { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, + { .compatible = "aspeed,ast2700-mac", .data = FTGMAC100_MODEL_ASPEED_AST2700 }, + {} }; U_BOOT_DRIVER(ftgmac100) = { diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index f7874ae..c38b57c 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -66,6 +66,13 @@ struct ftgmac100 { unsigned int rx_runt; /* 0xc0 */ unsigned int rx_crcer_ftl; /* 0xc4 */ unsigned int rx_col_lost; /* 0xc8 */ + unsigned int reserved[43]; /* 0xcc - 0x174 */ + unsigned int txr_badr_lo; /* 0x178, defined in ast2700 */ + unsigned int txr_badr_hi; /* 0x17c, defined in ast2700 */ + unsigned int hptxr_badr_lo; /* 0x180, defined in ast2700 */ + unsigned int hptxr_badr_hi; /* 0x184, defined in ast2700 */ + unsigned int rxr_badr_lo; /* 0x188, defined in ast2700 */ + unsigned int rxr_badr_hi; /* 0x18c, defined in ast2700 */ }; /* @@ -111,6 +118,7 @@ struct ftgmac100 { #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DESC_UNIT 8 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) #define FTGMAC100_DBLAC_IFG_INC BIT(23) @@ -157,6 +165,7 @@ struct ftgmac100 { #define FTGMAC100_MACCR_RX_BROADPKT BIT(17) #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) #define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_RMII_ENABLE BIT(20) /* defined in ast2700 */ #define FTGMAC100_MACCR_SW_RST BIT(31) /* @@ -183,7 +192,7 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) #define FTGMAC100_TXDES0_EDOTR BIT(15) @@ -201,6 +210,8 @@ struct ftgmac100_txdes { #define FTGMAC100_TXDES1_TX2FIC BIT(30) #define FTGMAC100_TXDES1_TXIC BIT(31) +#define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16) + /* * Receive descriptor, aligned to 16 bytes */ @@ -209,7 +220,7 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) #define FTGMAC100_RXDES0_EDORR BIT(15) @@ -240,4 +251,6 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) +#define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16) + #endif /* __FTGMAC100_H */ diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 199a072..fa0b3db 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -101,7 +101,6 @@ static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6]) /* set the ethernet address */ ftmac100_set_mac(priv, enetaddr); - /* disable all interrupts */ writel (0, &ftmac100->imr); diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index d63e2db..8cfeeff 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -51,7 +51,6 @@ struct rk_gmac_ops { void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata); }; - static int gmac_rockchip_of_to_plat(struct udevice *dev) { struct gmac_rockchip_plat *pdata = dev_get_plat(dev); diff --git a/drivers/net/ks8851_mll.h b/drivers/net/ks8851_mll.h index 7f90ae4..7c5da7d 100644 --- a/drivers/net/ks8851_mll.h +++ b/drivers/net/ks8851_mll.h @@ -114,7 +114,6 @@ #define TXSR_TXFID_SHIFT (0) #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) - #define KS_RXCR1 0x74 #define RXCR1_FRXQ (1 << 15) #define RXCR1_RXUDPFCC (1 << 14) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index af082e3..ac8d1e4 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -17,7 +17,6 @@ #include <fsl-mc/fsl_qbman_portal.h> #include <fsl-mc/fsl_mc_private.h> - enum ldpaa_eth_type { LDPAA_ETH_1G_E, LDPAA_ETH_10G_E, diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index a803b8f..7587592 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -52,7 +52,6 @@ void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if) } } - /*TODO what it do */ static int wriop_dpmac_to_index(int dpmac_id) { @@ -102,7 +101,6 @@ int wriop_is_enabled_dpmac(int dpmac_id) return dpmac_info[i].enabled; } - int wriop_set_mdio(int dpmac_id, struct mii_dev *bus) { int i = wriop_dpmac_to_index(dpmac_id); diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 72b84ae..0eb9057 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -273,7 +273,6 @@ #define GEM_SGMIIEN_OFFSET 27 #define GEM_SGMIIEN_SIZE 1 - /* Constants for data bus width. */ #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ @@ -303,7 +302,6 @@ #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ #define GEM_ADDR64_SIZE 1 - /* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ #define MACB_NSR_LINK_SIZE 1 @@ -456,7 +454,6 @@ #define GEM_TX_PKT_BUFF_OFFSET 21 #define GEM_TX_PKT_BUFF_SIZE 1 - /* Bitfields in DCFG5. */ #define GEM_TSU_OFFSET 8 #define GEM_TSU_SIZE 1 diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index c44fa6a..182f84c 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -636,7 +636,6 @@ static int fec_start(struct udevice *dev) return 0; } - static void fec_stop(struct udevice *dev) { struct ether_fcc_info_s *efis = dev_get_priv(dev); diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c index 2f3d091..1c58437 100644 --- a/drivers/net/mscc_eswitch/luton_switch.c +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -627,7 +627,6 @@ static int luton_probe(struct udevice *dev) GCB_MISC_STAT_PHY_READY, true, 500, false)) return -EACCES; - /* Initialize miim buses */ memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT); diff --git a/drivers/net/mscc_eswitch/mscc_miim.h b/drivers/net/mscc_eswitch/mscc_miim.h index feb1f40..b53fd30 100644 --- a/drivers/net/mscc_eswitch/mscc_miim.h +++ b/drivers/net/mscc_eswitch/mscc_miim.h @@ -20,5 +20,4 @@ struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count, phys_addr_t miim_base, unsigned long miim_size); - #endif /* _MSCC_MIIM_H_ */ diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 94f17a9..5098afe 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1964,7 +1964,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return -ENODEV; } - priv->pn_swap = ofnode_read_bool(args.node, "pn_swap"); + /* Upstream linux use mediatek,pnswap instead of pn_swap */ + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || + ofnode_read_bool(args.node, "mediatek,pnswap"); } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index f014d39..1640868 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -970,7 +970,6 @@ static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, return &pp->rxqs[rxq]; } - /* Drop packets received by the RXQ and free buffers */ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) @@ -1107,7 +1106,6 @@ static void mvneta_cleanup_rxqs(struct mvneta_port *pp) mvneta_rxq_deinit(pp, &pp->rxqs[queue]); } - /* Init all Rx queues */ static int mvneta_setup_rxqs(struct mvneta_port *pp) { diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index d19a79d..ae545fe 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4702,7 +4702,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) port->rxqs[queue] = rxq; } - /* Create Rx descriptor rings */ for (queue = 0; queue < rxq_number; queue++) { struct mvpp2_rx_queue *rxq = port->rxqs[queue]; diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index ce2f76e..651b8ae 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -164,7 +164,6 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv) if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) sgmii_2500 = 1; - /* PCS configuration done with corresponding GEMAC */ bus.priv = gem_info[priv->gemac_port].gemac_base; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 73064b2..a9efc50 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -368,6 +368,7 @@ config PHY_FIXED config PHY_NCSI bool "NC-SI based PHY" + depends on NET endif #PHYLIB diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c index 72d6681..52c7189 100644 --- a/drivers/net/phy/davicom.c +++ b/drivers/net/phy/davicom.c @@ -21,7 +21,6 @@ #define MIIM_DM9161_10BTCSR 0x12 #define MIIM_DM9161_10BTCSR_INIT 0x7800 - /* Davicom DM9161E */ static int dm9161_config(struct phy_device *phydev) { diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c index a817c58..6002050 100644 --- a/drivers/net/phy/lxt.c +++ b/drivers/net/phy/lxt.c @@ -15,7 +15,6 @@ #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ - /* LXT971 */ static int lxt971_parse_status(struct phy_device *phydev) { diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index 556d75e..c48ae6e 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -228,7 +228,6 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); } - static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, int regnum) { diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 083d9d3..b143137 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -279,7 +279,6 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) return rdreg; } - /***************************************************************************** * * Write a MII PHY register. diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c index 6284298..db4c91e 100644 --- a/drivers/net/phy/mv88e6352.c +++ b/drivers/net/phy/mv88e6352.c @@ -262,7 +262,6 @@ int do_mvsw_reg_write(const char *name, int argc, char *const argv[]) return ret; } - int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret; diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c index f7e514e..1a65e55 100644 --- a/drivers/net/phy/natsemi.c +++ b/drivers/net/phy/natsemi.c @@ -42,7 +42,6 @@ U_BOOT_PHY_DRIVER(dp83630) = { .shutdown = &genphy_shutdown, }; - /* DP83865 Link and Auto-Neg Status Register */ #define MIIM_DP83865_LANR 0x11 #define MIIM_DP83865_SPD_MASK 0x0018 @@ -50,7 +49,6 @@ U_BOOT_PHY_DRIVER(dp83630) = { #define MIIM_DP83865_SPD_100 0x0008 #define MIIM_DP83865_DPX_FULL 0x0002 - /* NatSemi DP83865 */ static int dp838xx_config(struct phy_device *phydev) { @@ -101,7 +99,6 @@ static int dp83865_startup(struct phy_device *phydev) return dp83865_parse_status(phydev); } - U_BOOT_PHY_DRIVER(dp83865) = { .name = "NatSemi DP83865", .uid = 0x20005c70, diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index e80aebc..edcae88 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -736,7 +736,6 @@ static void rtl8169_hw_start(struct udevice *dev) RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift)); - tpc->cur_rx = 0; RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, @@ -1031,7 +1030,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name, #endif } - tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); if (!tpc->RxDescArray) return -ENOMEM; diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 1c07610..ecf4a69 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -474,7 +474,6 @@ enum EESR_BIT { EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, }; - #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index f4b9779..0da182d 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -171,7 +171,6 @@ struct emac_eth_dev { struct udevice *phy_reg; }; - struct sun8i_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; @@ -179,7 +178,6 @@ struct sun8i_eth_pdata { int rx_delay_ps; }; - static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { struct udevice *dev = bus->priv; @@ -892,6 +890,11 @@ static const struct emac_variant emac_variant_r40 = { .syscon_offset = 0x164, }; +static const struct emac_variant emac_variant_v3s = { + .syscon_offset = 0x30, + .soc_has_internal_phy = true, +}; + static const struct emac_variant emac_variant_a64 = { .syscon_offset = 0x30, .support_rmii = true, @@ -909,6 +912,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (ulong)&emac_variant_h3 }, { .compatible = "allwinner,sun8i-r40-gmac", .data = (ulong)&emac_variant_r40 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = (ulong)&emac_variant_v3s }, { .compatible = "allwinner,sun50i-a64-emac", .data = (ulong)&emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 03a1a7a..d808519 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -144,7 +144,6 @@ static int davinci_emac_write_hwaddr(struct udevice *dev) writel(mac_hi, &adap_emac->MACSRCADDRHI); writel(mac_lo, &adap_emac->MACSRCADDRLO); - return 0; } @@ -205,7 +204,6 @@ static int davinci_eth_phy_detect(void) return count; } - /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) { @@ -378,7 +376,6 @@ static int gen_auto_negotiate(int phy_addr) } /* End of generic PHY functions */ - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, int reg) diff --git a/drivers/net/ti/davinci_emac.h b/drivers/net/ti/davinci_emac.h index 695855b..c213e24 100644 --- a/drivers/net/ti/davinci_emac.h +++ b/drivers/net/ti/davinci_emac.h @@ -20,7 +20,6 @@ */ #define EMAC_MAX_RX_BUFFERS 10 - /*********************************************** ******** Internally used macros *************** ***********************************************/ @@ -45,7 +44,6 @@ /* Number of statistics registers */ #define EMAC_NUM_STATS 36 - /* EMAC Descriptor */ typedef volatile struct _emac_desc { @@ -78,7 +76,6 @@ typedef volatile struct _emac_desc #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - #define MDIO_CONTROL_IDLE (0x80000000) #define MDIO_CONTROL_ENABLE (0x40000000) #define MDIO_CONTROL_FAULT_ENABLE (0x40000) diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index c6e5bf2..d4abc9a 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -83,7 +83,6 @@ enum link_type { #endif - struct ks2_eth_priv { struct udevice *dev; struct phy_device *phydev; @@ -208,7 +207,6 @@ int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); __raw_writel(control, SGMII_CTL_REG(port)); - mask = SGMII_REG_STATUS_LINK; if (control & SGMII_REG_CONTROL_AUTONEG) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b41ee95..461805a 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -228,7 +228,6 @@ struct zynq_gem_priv { struct clk tx_clk; struct clk pclk; u32 max_speed; - bool int_pcs; bool dma_64bit; u32 clk_en_info; struct reset_ctl_bulk resets; @@ -390,7 +389,6 @@ static int zynq_phy_init(struct udevice *dev) return phy_config(priv->phydev); } - static int zynq_gem_init(struct udevice *dev) { u32 i, nwconfig, nwcfg; @@ -505,8 +503,7 @@ static int zynq_gem_init(struct udevice *dev) * Set SGMII enable PCS selection only if internal PCS/PMA * core is used and interface is SGMII. */ - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | ZYNQ_GEM_NWCFG_PCS_SEL; } @@ -530,8 +527,7 @@ static int zynq_gem_init(struct udevice *dev) writel(nwcfg, ®s->nwcfg); #ifdef CONFIG_ARM64 - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { /* * Disable AN for fixed link configuration, enable otherwise. * Must be written after PCS_SEL is set in nwconfig, @@ -993,8 +989,6 @@ static int zynq_gem_of_to_plat(struct udevice *dev) return -EINVAL; priv->interface = pdata->phy_interface; - priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); - priv->clk_en_info = dev_get_driver_data(dev); return 0; |