diff options
Diffstat (limited to 'drivers/clk')
161 files changed, 217 insertions, 1337 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9acbc47..bda6873 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -246,7 +246,6 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform. -source "drivers/clk/adi/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 847b9b2..638ad04 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,7 +12,6 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o -obj-y += adi/ obj-y += analogbits/ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig deleted file mode 100644 index 5745bed..0000000 --- a/drivers/clk/adi/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> -# Contact: Greg Malysa <greg.malysa@timesys.com> -# - -config COMMON_CLK_ADI_SHARED - bool "Enable shared ADI clock framework code" - help - Required for shared code between SoC clock drivers. Automatically - selected by an appropriate SoC-specific clock driver version. - -config COMMON_CLK_ADI_SC598 - bool "Clock driver for ADI SC598 SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select SPL_DM if SPL - select SPL_CLK if SPL - select SPL_CLK_CCF if SPL - select SPL_OF_CONTROL if SPL - select COMMON_CLK_ADI_SHARED - depends on SC59X_64 - help - This driver supports the system clocks on Analog Devices SC598-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. - -config COMMON_CLK_ADI_SC594 - bool "Clock driver for ADI SC594 SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select SPL_DM if SPL - select SPL_CLK if SPL - select SPL_CLK_CCF if SPL - select SPL_OF_CONTROL if SPL - select COMMON_CLK_ADI_SHARED - depends on SC59X - help - This driver supports the system clocks on Analog Devices SC594-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. - -config COMMON_CLK_ADI_SC58X - bool "Clock driver for ADI SC58X SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select COMMON_CLK_ADI_SHARED - depends on SC58X - help - This driver supports the system clocks on Analog Devices SC58x-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. - -config COMMON_CLK_ADI_SC57X - bool "Clock driver for ADI SC57X SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select COMMON_CLK_ADI_SHARED - depends on SC57X - help - This driver supports the system clocks on Analog Devices SC57x-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. diff --git a/drivers/clk/adi/Makefile b/drivers/clk/adi/Makefile deleted file mode 100644 index f3f1fd9..0000000 --- a/drivers/clk/adi/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> -# Contact: Greg Malysa <greg.malysa@timesys.com> -# - -obj-$(CONFIG_COMMON_CLK_ADI_SHARED) += clk-shared.o clk-adi-pll.o - -obj-$(CONFIG_COMMON_CLK_ADI_SC594) += clk-adi-sc594.o -obj-$(CONFIG_COMMON_CLK_ADI_SC598) += clk-adi-sc598.o -obj-$(CONFIG_COMMON_CLK_ADI_SC58X) += clk-adi-sc58x.o -obj-$(CONFIG_COMMON_CLK_ADI_SC57X) += clk-adi-sc57x.o diff --git a/drivers/clk/adi/clk-adi-pll.c b/drivers/clk/adi/clk-adi-pll.c deleted file mode 100644 index 372baa9..0000000 --- a/drivers/clk/adi/clk-adi-pll.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - * - * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com> - */ - -#include <clk.h> -#include <clk-uclass.h> -#include <asm/io.h> -#include <dm/device.h> -#include <linux/compiler_types.h> -#include <linux/err.h> -#include <linux/kernel.h> - -#include "clk.h" - -#define ADI_CLK_PLL_GENERIC "adi_clk_pll_generic" - -struct clk_sc5xx_cgu_pll { - struct clk clk; - void __iomem *base; - u32 mask; - u32 max; - u32 m_offset; - u8 shift; - bool half_m; -}; - -#define to_clk_sc5xx_cgu_pll(_clk) container_of(_clk, struct clk_sc5xx_cgu_pll, clk) - -static unsigned long sc5xx_cgu_pll_get_rate(struct clk *clk) -{ - struct clk_sc5xx_cgu_pll *pll = to_clk_sc5xx_cgu_pll(dev_get_clk_ptr(clk->dev)); - unsigned long parent_rate = clk_get_parent_rate(clk); - - u32 reg = readl(pll->base); - u32 m = ((reg & pll->mask) >> pll->shift) + pll->m_offset; - - if (m == 0) - m = pll->max; - - if (pll->half_m) - return parent_rate * m * 2; - return parent_rate * m; -} - -static const struct clk_ops clk_sc5xx_cgu_pll_ops = { - .get_rate = sc5xx_cgu_pll_get_rate, -}; - -struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name, - void __iomem *base, u8 shift, u8 width, u32 m_offset, - bool half_m) -{ - struct clk_sc5xx_cgu_pll *pll; - struct clk *clk; - int ret; - char *drv_name = ADI_CLK_PLL_GENERIC; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) - return ERR_PTR(-ENOMEM); - - pll->base = base; - pll->shift = shift; - pll->mask = GENMASK(width - 1, 0) << shift; - pll->max = pll->mask + 1; - pll->m_offset = m_offset; - pll->half_m = half_m; - - clk = &pll->clk; - - ret = clk_register(clk, drv_name, name, parent_name); - if (ret) { - pr_err("Failed to register %s in %s: %d\n", name, __func__, ret); - kfree(pll); - return ERR_PTR(ret); - } - - return clk; -} - -U_BOOT_DRIVER(clk_adi_pll_generic) = { - .name = ADI_CLK_PLL_GENERIC, - .id = UCLASS_CLK, - .ops = &clk_sc5xx_cgu_pll_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc57x.c b/drivers/clk/adi/clk-adi-sc57x.c deleted file mode 100644 index b17563f..0000000 --- a/drivers/clk/adi/clk-adi-sc57x.c +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - * - * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com> - */ - -#include <clk.h> -#include <clk-uclass.h> -#include <dm.h> -#include <dt-bindings/clock/adi-sc5xx-clock.h> -#include <linux/compiler_types.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/printk.h> -#include <linux/types.h> - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "oclk_0_half"}; -static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"}; -static const char * const gige_sels[] = {"sclk1_0", "sclk1_1", "cclk0_1", "oclk_0"}; -static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1", - "dclk_1"}; - -static int sc57x_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC57X_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC57X_CLK_DUMMY] = &dummy; - clks[ADSP_SC57X_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC57X_CLK_SYS_CLKIN1] = &clkin1; - - clks[ADSP_SC57X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // CGU configuration and internal clocks - clks[ADSP_SC57X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC57X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - - // VCO output == PLL output - clks[ADSP_SC57X_CLK_CGU0_PLLCLK] = sc5xx_cgu_pll("cgu0_pllclk", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - clks[ADSP_SC57X_CLK_CGU1_PLLCLK] = sc5xx_cgu_pll("cgu1_pllclk", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - - // Dividers from pll output - clks[ADSP_SC57X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC57X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC57X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC57X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC57X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC57X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - - clks[ADSP_SC57X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC57X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC57X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC57X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC57X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", - "sysclk_1", cgu1 + CGU_DIV, 5, - 3, 0); - clks[ADSP_SC57X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", - "sysclk_1", cgu1 + CGU_DIV, 13, - 3, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC57X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC57X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC57X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC57X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC57X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC57X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC57X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC57X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", - cgu1 + CGU_SCBF_DIS, 0); - - // Extra half rate clocks generated in the CDU - clks[ADSP_SC57X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half", - "oclk_0", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC57X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL, - "cclk1_1_half", - "cclk1_1", - CLK_SET_RATE_PARENT, - 1, 2); - - // CDU output muxes - clks[ADSP_SC57X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC57X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC57X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC57X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC57X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC57X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC57X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC57X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels); - - // CDU output enable gates - clks[ADSP_SC57X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC57X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC57X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC57X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc57x_clk_ids[] = { - { .compatible = "adi,sc57x-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc57x_clk) = { - .name = "clk_adi_sc57x", - .id = UCLASS_CLK, - .of_match = adi_sc57x_clk_ids, - .ops = &adi_clk_ops, - .probe = sc57x_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc58x.c b/drivers/clk/adi/clk-adi-sc58x.c deleted file mode 100644 index 05a0fed..0000000 --- a/drivers/clk/adi/clk-adi-sc58x.c +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - * - * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com> - */ - -#include <clk.h> -#include <clk-uclass.h> -#include <dm.h> -#include <dt-bindings/clock/adi-sc5xx-clock.h> -#include <linux/compiler_types.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/printk.h> -#include <linux/types.h> - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dummy"}; -static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"}; -static const char * const reserved_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; -static const char * const gige_sels[] = {"sclk0_0", "sclk1_1", "cclk0_1", "oclk_0"}; -static const char * const lp_sels[] = {"sclk0_0", "sclk0_1", "cclk1_1", "dclk_1"}; -static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1", - "dclk_1"}; - -static int sc58x_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC58X_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC58X_CLK_DUMMY] = &dummy; - clks[ADSP_SC58X_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC58X_CLK_SYS_CLKIN1] = &clkin1; - - clks[ADSP_SC58X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // CGU configuration and internal clocks - clks[ADSP_SC58X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC58X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - - // VCO output inside PLL - clks[ADSP_SC58X_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - clks[ADSP_SC58X_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - - // Final PLL output - clks[ADSP_SC58X_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 1); - clks[ADSP_SC58X_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 1); - - // Dividers from pll output - clks[ADSP_SC58X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC58X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC58X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC58X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC58X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC58X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - - clks[ADSP_SC58X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC58X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC58X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC58X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC58X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", - cgu1 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC58X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", - cgu1 + CGU_DIV, 13, 3, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC58X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC58X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC58X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC58X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC58X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC58X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC58X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC58X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", - cgu1 + CGU_SCBF_DIS, 0); - - // Extra half rate clocks generated in the CDU - clks[ADSP_SC58X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half", - "oclk_0", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC58X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL, - "cclk1_1_half", - "cclk1_1", - CLK_SET_RATE_PARENT, - 1, 2); - - // CDU output muxes - clks[ADSP_SC58X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC58X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC58X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC58X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC58X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC58X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC58X_CLK_RESERVED_SEL] = cdu_mux("reserved_sel", cdu + CDU_CFG6, - reserved_sels); - clks[ADSP_SC58X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC58X_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); - clks[ADSP_SC58X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels); - - // CDU output enable gates - clks[ADSP_SC58X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC58X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC58X_CLK_RESERVED] = cdu_gate("reserved", "reserved_sel", - cdu + CDU_CFG6, 0); - clks[ADSP_SC58X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC58X_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); - clks[ADSP_SC58X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc58x_clk_ids[] = { - { .compatible = "adi,sc58x-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc58x_clk) = { - .name = "clk_adi_sc58x", - .id = UCLASS_CLK, - .of_match = adi_sc58x_clk_ids, - .ops = &adi_clk_ops, - .probe = sc58x_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc594.c b/drivers/clk/adi/clk-adi-sc594.c deleted file mode 100644 index c80bbf9..0000000 --- a/drivers/clk/adi/clk-adi-sc594.c +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - * - * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com> - */ - -#include <clk.h> -#include <clk-uclass.h> -#include <dm.h> -#include <dt-bindings/clock/adi-sc5xx-clock.h> -#include <linux/compiler_types.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/printk.h> -#include <linux/types.h> - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"}; -static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"}; -static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const arm_sels[] = {"cclk1_0", "dummy", "dummy", "dummy"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"oclk_0", "oclk_1", "dummy", "dummy"}; -static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"}; -static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; -static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "cclk0_1", "dummy"}; -static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"}; -static const char * const lpddr_sels[] = {"oclk_0", "dclk_0", "sysclkin_1", "dummy"}; -static const char * const ospi_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", "dummy"}; -static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"}; - -static int sc594_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC594_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC594_CLK_DUMMY] = &dummy; - clks[ADSP_SC594_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC594_CLK_SYS_CLKIN1] = &clkin1; - clks[ADSP_SC594_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // CGU configuration and internal clocks - clks[ADSP_SC594_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC594_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - - // VCO output inside PLL - clks[ADSP_SC594_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - clks[ADSP_SC594_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - - // Final PLL output - clks[ADSP_SC594_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 1); - clks[ADSP_SC594_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 1); - - // Dividers from pll output - clks[ADSP_SC594_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC594_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC594_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC594_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC594_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC594_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC594_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", - "cgu0_pllclk", - cgu0 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC594_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", - cgu0_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 17, 1, 0); - - clks[ADSP_SC594_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC594_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC594_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC594_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC594_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", - cgu1 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC594_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", - cgu1 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC594_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", - "cgu1_pllclk", - cgu1 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC594_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel", - cgu1_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 17, 1, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC594_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC594_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC594_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC594_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC594_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC594_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC594_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC594_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", - cgu1 + CGU_SCBF_DIS, 0); - - // CDU output muxes - clks[ADSP_SC594_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC594_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC594_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC594_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC594_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC594_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC594_CLK_RESERVED_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels); - clks[ADSP_SC594_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC594_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); - clks[ADSP_SC594_CLK_LPDDR_SEL] = cdu_mux("lpddr_sel", cdu + CDU_CFG9, lpddr_sels); - clks[ADSP_SC594_CLK_OSPI_SEL] = cdu_mux("ospi_sel", cdu + CDU_CFG10, - ospi_sels); - clks[ADSP_SC594_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12, - trace_sels); - - // CDU output enable gates - clks[ADSP_SC594_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", - cdu + CDU_CFG0, CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", - cdu + CDU_CFG1, CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", - cdu + CDU_CFG3, CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC594_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC594_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0); - clks[ADSP_SC594_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC594_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); - clks[ADSP_SC594_CLK_LPDDR] = cdu_gate("lpddr", "lpddr_sel", cdu + CDU_CFG9, 0); - clks[ADSP_SC594_CLK_OSPI] = cdu_gate("ospi", "ospi_sel", cdu + CDU_CFG10, 0); - clks[ADSP_SC594_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc594_clk_ids[] = { - { .compatible = "adi,sc594-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc594_clk) = { - .name = "clk_adi_sc594", - .id = UCLASS_CLK, - .of_match = adi_sc594_clk_ids, - .ops = &adi_clk_ops, - .probe = sc594_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc598.c b/drivers/clk/adi/clk-adi-sc598.c deleted file mode 100644 index d4a16ac..0000000 --- a/drivers/clk/adi/clk-adi-sc598.c +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - * - * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com> - */ - -#include <clk.h> -#include <clk-uclass.h> -#include <dm.h> -#include <dt-bindings/clock/adi-sc5xx-clock.h> -#include <linux/compiler_types.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/printk.h> -#include <linux/types.h> - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"}; -static const char * const cgu1_s0sels[] = {"cgu1_s0seldiv", "cgu1_s0selexdiv"}; -static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"}; -static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const arm_sels[] = {"dummy", "dummy", "cclk2_0", "cclk2_1"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"dummy", "oclk_1", "dummy", "dummy"}; -static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"}; -static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; -static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "dummy", "dummy"}; -static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"}; -static const char * const lp_ddr_sels[] = {"oclk_0", "dclk_0", "sysclk_1", "dummy"}; -static const char * const ospi_refclk_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", - "dummy"}; -static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"}; -static const char * const emmc_sels[] = {"oclk_0", "sclk0_1", "dclk_0_half", - "dclk_1_half"}; -static const char * const emmc_timer_sels[] = {"dummy", "sclk1_1_half", "dummy", - "dummy"}; -static const char * const ddr_sels[] = {"cdu_ddr", "3pll_ddiv"}; - -static int sc598_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - void __iomem *pll3; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC598_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "pll3", &res); - if (ret) - return ret; - pll3 = devm_ioremap(dev, res.start, resource_size(&res)); - - // We only access this one register for pll3 - pll3 = pll3 + PLL3_OFFSET; - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC598_CLK_DUMMY] = &dummy; - clks[ADSP_SC598_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC598_CLK_SYS_CLKIN1] = &clkin1; - - clks[ADSP_SC598_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // 3rd pll reuses cgu1 clk in selection, feeds directly into 3pll df - // changing the cgu1 in sel mux will affect 3pll so reuse the same clocks - - // CGU configuration and internal clocks - clks[ADSP_SC598_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC598_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC598_CLK_3PLL_PLL_IN] = clk_register_divider(NULL, "3pll_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - pll3, 3, 1, 0); - - // VCO output inside PLL - clks[ADSP_SC598_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, true); - clks[ADSP_SC598_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, true); - clks[ADSP_SC598_CLK_3PLL_VCO_OUT] = sc5xx_cgu_pll("3pll_vco", "3pll_df", - pll3, PLL3_MSEL_SHIFT, - PLL3_MSEL_WIDTH, 1, true); - - // Final PLL output - clks[ADSP_SC598_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_3PLL_PLLCLK] = clk_register_fixed_factor(NULL, "3pll_pllclk", - "3pll_vco", - CLK_SET_RATE_PARENT, - 1, 2); - - // Dividers from pll output - clks[ADSP_SC598_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC598_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC598_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC598_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC598_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC598_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC598_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", - "cgu0_pllclk", - cgu0 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC598_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", - cgu0_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 17, 1, 0); - clks[ADSP_SC598_CLK_CGU0_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_0", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 3); - - clks[ADSP_SC598_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC598_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC598_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC598_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC598_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", - cgu1 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC598_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", - cgu1 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC598_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv", - "cgu1_pllclk", - cgu1 + CGU_DIVEX, 0, 8, 0); - clks[ADSP_SC598_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", - "cgu1_pllclk", - cgu1 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC598_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel", - cgu1_s0sels, 2, - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 16, 1, 0); - clks[ADSP_SC598_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel", - cgu1_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 17, 1, 0); - clks[ADSP_SC598_CLK_CGU1_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_1", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 3); - - clks[ADSP_SC598_CLK_3PLL_DDIV] = clk_register_divider(NULL, "3pll_ddiv", - "3pll_pllclk", - CLK_SET_RATE_PARENT, pll3, - 12, 5, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC598_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC598_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC598_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC598_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC598_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC598_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC598_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC598_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC598_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC598_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_sclk0sel", - cgu1 + CGU_SCBF_DIS, 0); - - // Extra half rate clocks generated in the CDU - clks[ADSP_SC598_CLK_DCLK0_HALF] = clk_register_fixed_factor(NULL, "dclk_0_half", - "dclk_0", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_DCLK1_HALF] = clk_register_fixed_factor(NULL, "dclk_1_half", - "dclk_1", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_CGU1_SCLK1_HALF] = clk_register_fixed_factor(NULL, - "sclk1_1_half", - "sclk1_1", - CLK_SET_RATE_PARENT, - 1, 2); - - // CDU output muxes - clks[ADSP_SC598_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC598_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC598_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC598_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC598_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC598_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC598_CLK_SPI_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels); - clks[ADSP_SC598_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC598_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); - clks[ADSP_SC598_CLK_LP_DDR_SEL] = cdu_mux("lp_ddr_sel", cdu + CDU_CFG9, - lp_ddr_sels); - clks[ADSP_SC598_CLK_OSPI_REFCLK_SEL] = cdu_mux("ospi_refclk_sel", cdu + CDU_CFG10, - ospi_refclk_sels); - clks[ADSP_SC598_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12, - trace_sels); - clks[ADSP_SC598_CLK_EMMC_SEL] = cdu_mux("emmc_sel", cdu + CDU_CFG13, emmc_sels); - clks[ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL] = cdu_mux("emmc_timer_qmc_sel", - cdu + CDU_CFG14, - emmc_timer_sels); - - // CDU output enable gates - clks[ADSP_SC598_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, - CLK_IS_CRITICAL); - clks[ADSP_SC598_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, - CLK_IS_CRITICAL); - clks[ADSP_SC598_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC598_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, - 0); - clks[ADSP_SC598_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC598_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC598_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0); - clks[ADSP_SC598_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC598_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); - clks[ADSP_SC598_CLK_LP_DDR] = cdu_gate("lp_ddr", "lp_ddr_sel", cdu + CDU_CFG9, 0); - clks[ADSP_SC598_CLK_OSPI_REFCLK] = cdu_gate("ospi_refclk", "ospi_refclk_sel", - cdu + CDU_CFG10, 0); - clks[ADSP_SC598_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0); - clks[ADSP_SC598_CLK_EMMC] = cdu_gate("emmc", "emmc_sel", cdu + CDU_CFG13, 0); - clks[ADSP_SC598_CLK_EMMC_TIMER_QMC] = cdu_gate("emmc_timer_qmc", - "emmc_timer_qmc_sel", - cdu + CDU_CFG14, 0); - - // Dedicated DDR output mux - clks[ADSP_SC598_CLK_DDR] = clk_register_mux(NULL, "ddr", ddr_sels, 2, - CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - pll3, 11, 1, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc598_clk_ids[] = { - { .compatible = "adi,sc598-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc598_clk) = { - .name = "clk_adi_sc598", - .id = UCLASS_CLK, - .of_match = adi_sc598_clk_ids, - .ops = &adi_clk_ops, - .probe = sc598_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c deleted file mode 100644 index dcadcaf..0000000 --- a/drivers/clk/adi/clk-shared.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - */ - -#include "clk.h" - -static ulong adi_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong adi_set_rate(struct clk *clk, ulong rate) -{ - //Not yet implemented - return 0; -} - -static int adi_enable(struct clk *clk) -{ - //Not yet implemented - return 0; -} - -static int adi_disable(struct clk *clk) -{ - //Not yet implemented - return 0; -} - -const struct clk_ops adi_clk_ops = { - .set_rate = adi_set_rate, - .get_rate = adi_get_rate, - .enable = adi_enable, - .disable = adi_disable, -}; - diff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h deleted file mode 100644 index f230205..0000000 --- a/drivers/clk/adi/clk.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa <greg.malysa@timesys.com> - * - * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com> - */ - -#ifndef CLK_ADI_CLK_H -#define CLK_ADI_CLK_H - -#include <linux/compiler_types.h> -#include <linux/types.h> -#include <linux/clk-provider.h> - -#define CGU_CTL 0x00 -#define CGU_PLLCTL 0x04 -#define CGU_STAT 0x08 -#define CGU_DIV 0x0C -#define CGU_CLKOUTSEL 0x10 -#define CGU_OSCWDCTL 0x14 -#define CGU_TSCTL 0x18 -#define CGU_TSVALUE0 0x1C -#define CGU_TSVALUE1 0x20 -#define CGU_TSCOUNT0 0x24 -#define CGU_TSCOUNT1 0x28 -#define CGU_CCBF_DIS 0x2C -#define CGU_CCBF_STAT 0x30 -#define CGU_SCBF_DIS 0x38 -#define CGU_SCBF_STAT 0x3C -#define CGU_DIVEX 0x40 -#define CGU_REVID 0x48 - -#define CDU_CFG0 0x00 -#define CDU_CFG1 0x04 -#define CDU_CFG2 0x08 -#define CDU_CFG3 0x0C -#define CDU_CFG4 0x10 -#define CDU_CFG5 0x14 -#define CDU_CFG6 0x18 -#define CDU_CFG7 0x1C -#define CDU_CFG8 0x20 -#define CDU_CFG9 0x24 -#define CDU_CFG10 0x28 -#define CDU_CFG11 0x2C -#define CDU_CFG12 0x30 -#define CDU_CFG13 0x34 -#define CDU_CFG14 0x38 - -#define PLL3_OFFSET 0x2c - -#define CDU_CLKINSEL 0x44 - -#define CGU_MSEL_SHIFT 8 -#define CGU_MSEL_WIDTH 7 - -#define PLL3_MSEL_SHIFT 4 -#define PLL3_MSEL_WIDTH 7 - -#define CDU_MUX_SIZE 4 -#define CDU_MUX_SHIFT 1 -#define CDU_MUX_WIDTH 2 -#define CDU_EN_BIT 0 - -extern const struct clk_ops adi_clk_ops; - -struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name, - void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m); - -/** - * All CDU clock muxes are the same size - */ -static inline struct clk *cdu_mux(const char *name, void __iomem *reg, - const char * const *parents) -{ - return clk_register_mux(NULL, name, parents, CDU_MUX_SIZE, - CLK_SET_RATE_PARENT, reg, CDU_MUX_SHIFT, CDU_MUX_WIDTH, 0); -} - -static inline struct clk *cgu_divider(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width, u8 extra_flags) -{ - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, - reg, shift, width, CLK_DIVIDER_MAX_AT_ZERO | extra_flags); -} - -static inline struct clk *cdu_gate(const char *name, const char *parent, - void __iomem *reg, u32 flags) -{ - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | flags, - reg, CDU_EN_BIT, 0, NULL); -} - -static inline struct clk *cgu_gate(const char *name, const char *parent, - void __iomem *reg, u8 bit) -{ - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, bit, - CLK_GATE_SET_TO_DISABLE, NULL); -} - -static inline int cdu_check_clocks(struct clk *clks[], size_t count) -{ - size_t i; - - for (i = 0; i < count; ++i) { - if (clks[i]) { - if (IS_ERR(clks[i])) { - pr_err("Clock %zu failed to register: %ld\n", i, PTR_ERR(clks[i])); - return PTR_ERR(clks[i]); - } - clks[i]->id = i; - } else { - pr_err("ADI Clock framework: Null pointer detected on clock %zu\n", i); - } - } - - return 0; -} - -#endif diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index bdc7be0..cca6d67 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation <www.intel.com> */ +#include <common.h> #include <log.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 72b9234..92f2abd 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -15,6 +15,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/system.h> +#include <asm/u-boot.h> #include <dm/lists.h> #include <dm/util.h> #include <linux/bitops.h> diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index 1840f73..578597a 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Marek Vasut <marex@denx.de> */ +#include <common.h> #include <malloc.h> #include <asm/io.h> #include <clk-uclass.h> diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index b75f52d..9bbe2cd 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -3,6 +3,7 @@ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> */ +#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 3e25610..3fa19e0 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -3,6 +3,7 @@ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> */ +#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index a330dcd..dc446ce 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Google, Inc */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 535010b..a159093 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -3,6 +3,7 @@ * Copyright (C) ASPEED Technology Inc. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <asm/io.h> diff --git a/drivers/clk/at91/clk-generic.c b/drivers/clk/at91/clk-generic.c index c410cd2..87738b7 100644 --- a/drivers/clk/at91/clk-generic.c +++ b/drivers/clk/at91/clk-generic.c @@ -8,6 +8,7 @@ * * Based on drivers/clk/at91/clk-generated.c from Linux. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/io.h> diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 09daae9..025c7a7 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -10,6 +10,7 @@ */ #include <asm/processor.h> +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index d28775d..aec0bca 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <clk-uclass.h> +#include <common.h> #include <div64.h> #include <dm.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 08d7e7d..52cbc52 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -8,6 +8,7 @@ * * Based on drivers/clk/at91/clk-peripheral.c from Linux. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/io.h> diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index d0b1465..868de4b 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -8,6 +8,7 @@ * * Based on drivers/clk/at91/clk-programmable.c from Linux. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index a30035e..383f79c 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -11,6 +11,7 @@ */ #include <asm/processor.h> +#include <common.h> #include <clk-uclass.h> #include <div64.h> #include <dm.h> diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 3545b0b..82f79e7 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -9,6 +9,7 @@ * Based on drivers/clk/at91/clk-system.c from Linux. */ #include <asm/processor.h> +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/io.h> diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index 84784ae..7c8bcfb 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -9,6 +9,7 @@ * Based on drivers/clk/at91/clk-utmi.c from Linux. */ #include <asm/processor.h> +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index 1d738f1..ee67093 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -6,7 +6,7 @@ * * Author: Claudiu Beznea <claudiu.beznea@microchip.com> */ -#include <config.h> +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <asm/global_data.h> diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index aa4bc8f..87d2069 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -4,6 +4,7 @@ * Wenyou.Yang <wenyou.yang@atmel.com> */ +#include <common.h> #include <asm/io.h> #include <clk-uclass.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index b7d64bd..d858c86 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -7,6 +7,7 @@ * Based on sam9x60.c on Linux. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-bindings/clk/at91.h> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 63b2c64..3e62fb1 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -9,6 +9,7 @@ * Based on drivers/clk/at91/sama7g5.c from Linux. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-bindings/clk/at91.h> diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 6d6f125..43136ab 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -7,6 +7,7 @@ * Author: Claudiu Beznea <claudiu.beznea@microchip.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-bindings/clk/at91.h> diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c index e5f74e7..b8700f5 100644 --- a/drivers/clk/clk-cdce9xx.c +++ b/drivers/clk/clk-cdce9xx.c @@ -8,6 +8,7 @@ * Based on Linux kernel clk-cdce925.c. */ +#include <common.h> #include <dm.h> #include <errno.h> #include <clk-uclass.h> diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 199ca6e..d2e5a1a 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <log.h> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index aa210e3..2ad682b 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 068798c..2a44678 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <div64.h> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index bf1c6a9..cfd90b7 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <log.h> #include <clk-uclass.h> diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 5365505..85074f1 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -9,6 +9,7 @@ * warranty of any kind, whether express or implied. */ +#include <common.h> #include <clk-uclass.h> #include <div64.h> #include <dm.h> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 39e01c3..f410518 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -23,6 +23,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <log.h> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 4c832f1..ed6e60b 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 4a3f50c..a10a843 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -7,6 +7,7 @@ * Author: Zhengxun Li <zhengxunli@mxic.com.tw> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <div64.h> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index b8c2e8d..6ede1b4 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <log.h> diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c index 0b41872..8c22ed2 100644 --- a/drivers/clk/clk_bcm6345.c +++ b/drivers/clk/clk_bcm6345.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c index 030ff7c..4bcf911 100644 --- a/drivers/clk/clk_boston.c +++ b/drivers/clk/clk_boston.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Imagination Technologies */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-bindings/clock/boston-clock.h> diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c index 1d740cf..6c1139e 100644 --- a/drivers/clk/clk_fixed_factor.c +++ b/drivers/clk/clk_fixed_factor.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <div64.h> #include <dm.h> diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index d1da05c..b5e78c7 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index d1a6cde..7432ae8 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -4,6 +4,7 @@ */ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <div64.h> diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c index 885aa83..a77d0e7 100644 --- a/drivers/clk/clk_pic32.c +++ b/drivers/clk/clk_pic32.c @@ -4,6 +4,7 @@ * */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <div64.h> diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c index 8dd77f1..73d943f 100644 --- a/drivers/clk/clk_sandbox.c +++ b/drivers/clk/clk_sandbox.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index f96a15c..38184e2 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -6,6 +6,7 @@ * Common Clock Framework [CCF] driver for Sandbox */ +#include <common.h> #include <dm.h> #include <clk.h> #include <malloc.h> diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index 8735021..c224dc1 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include <common.h> #include <dm.h> #include <clk.h> #include <malloc.h> diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index e42d203..34a4936 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <scmi_agent.h> diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c index 9ccaf13..bbe7225 100644 --- a/drivers/clk/clk_versaclock.c +++ b/drivers/clk/clk_versaclock.c @@ -5,6 +5,7 @@ * Derived from code Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 35ee56d..42ab032 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -4,6 +4,7 @@ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ +#include <common.h> #include <log.h> #include <asm/cache.h> #include <asm/ptrace.h> diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c index 2e0e7bb..3b1e020 100644 --- a/drivers/clk/clk_vexpress_osc.c +++ b/drivers/clk/clk_vexpress_osc.c @@ -5,6 +5,7 @@ * */ #define DEBUG +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index b62b464..e3cefe2 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -7,6 +7,7 @@ * Copyright (C) 2013 Xilinx, Inc. All rights reserved. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 5999926..e23f7da 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -5,6 +5,7 @@ * Copyright (C) 2016 Xilinx, Inc. */ +#include <common.h> #include <log.h> #include <malloc.h> #include <dm/device_compat.h> diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 3aa751b..9caa932 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -5,6 +5,7 @@ * Thomas Abraham <thomas.ab@samsung.com> */ +#include <common.h> #include <dm.h> #include <errno.h> #include <clk-uclass.h> diff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c index 9c61a84..33fb6ed 100644 --- a/drivers/clk/ics8n3qv01.c +++ b/drivers/clk/ics8n3qv01.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ +#include <common.h> #include <dm.h> #include <clk-uclass.h> #include <i2c.h> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 45f1bca..4941567 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include <common.h> #include <log.h> #include <asm/io.h> #include <malloc.h> diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c index 2cf20be..6d71c0c 100644 --- a/drivers/clk/imx/clk-composite-93.c +++ b/drivers/clk/imx/clk-composite-93.c @@ -4,6 +4,7 @@ * * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <log.h> #include <asm/io.h> #include <malloc.h> diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 8f42a5c..9228f27 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP */ +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c index d7f2640..bc85741 100644 --- a/drivers/clk/imx/clk-gate-93.c +++ b/drivers/clk/imx/clk-gate-93.c @@ -5,6 +5,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 65fa6b5..da27230 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -14,6 +14,7 @@ * */ +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ba9923d..67825af 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index 96cf5fe..d39b87b 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -4,6 +4,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 70e2e53..1a00dd1 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -4,6 +4,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ed9e16d..457acb8 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -4,6 +4,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1f498b6..7dfc829 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -4,6 +4,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index ed4acd7..cf197df 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -5,6 +5,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e..01e33de 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -4,6 +4,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08..d900d4c 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -4,6 +4,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index ede36c4..f0cb797 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP. */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index c80b029..dc91ac5 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 754f394..d40635d 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 20b9dc3..077dd1b 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -4,6 +4,7 @@ * Author(s): Jesse Taube <Mr.Bossman075@gmail.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 378cdff..b8be316 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -14,6 +14,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 3911e03..1cb685e 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -5,6 +5,7 @@ * Peng Fan <peng.fan@nxp.com> */ +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index c6692f2..fad306a 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include <common.h> #include <asm/io.h> #include <div64.h> #include <malloc.h> diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c index a677a7c..46ccbb1 100644 --- a/drivers/clk/intel/clk_intel.c +++ b/drivers/clk/intel/clk_intel.c @@ -4,6 +4,7 @@ * Written by Simon Glass <sjg@chromium.org> */ +#include <common.h> #include <dm.h> #include <clk-uclass.h> #include <dt-bindings/clock/intel-clock.h> diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2beb630..259ea33 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -6,6 +6,7 @@ * Author: Ryder Lee <ryder.lee@mediatek.com> */ +#include <common.h> #include <dm.h> #include <log.h> #include <asm/arch-mediatek/reset.h> diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 5072c99..0c7411e 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -6,6 +6,7 @@ * Author: Ryder Lee <ryder.lee@mediatek.com> */ +#include <common.h> #include <dm.h> #include <log.h> #include <asm/arch-mediatek/reset.h> diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 0c796a1..31b6fa0 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -6,6 +6,7 @@ * Author: Ryder Lee <ryder.lee@mediatek.com> */ +#include <common.h> #include <dm.h> #include <log.h> #include <asm/arch-mediatek/reset.h> diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 9612a62..17e653a 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -8,6 +8,7 @@ * Author: Weiyi Lu <weiyi.lu@mediatek.com> */ +#include <common.h> #include <dm.h> #include <asm/io.h> #include <dt-bindings/clock/mt8183-clk.h> diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index ab27067..193e069 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -6,6 +6,7 @@ * Author: Chen Zhong <chen.zhong@mediatek.com> */ +#include <common.h> #include <dm.h> #include <asm/io.h> #include <dt-bindings/clock/mt8512-clk.h> diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 623f884..29f7062 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -6,6 +6,7 @@ * Author: Fabien Parent <fparent@baylibre.com> */ +#include <common.h> #include <dm.h> #include <asm/io.h> #include <dt-bindings/clock/mt8516-clk.h> diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index ba8cc58..2386514 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -6,6 +6,7 @@ * Author: Chen Zhong <chen.zhong@mediatek.com> */ +#include <common.h> #include <dm.h> #include <asm/io.h> #include <dt-bindings/clock/mt8518-clk.h> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d2c45be..4303300 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -6,6 +6,7 @@ * Author: Ryder Lee <ryder.lee@mediatek.com> */ +#include <common.h> #include <clk-uclass.h> #include <div64.h> #include <dm.h> diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index a1b8d79..5220a33 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -4,6 +4,7 @@ * Author: Igor Prusov <ivprusov@salutedevices.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <regmap.h> diff --git a/drivers/clk/meson/axg-ao.c b/drivers/clk/meson/axg-ao.c index 6ccf521..311ffc1 100644 --- a/drivers/clk/meson/axg-ao.c +++ b/drivers/clk/meson/axg-ao.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <common.h> #include <log.h> #include <asm/io.h> #include <clk-uclass.h> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index c421a62..d6da59d 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -5,6 +5,7 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ +#include <common.h> #include <log.h> #include <asm/arch/clock-axg.h> #include <asm/io.h> diff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c index 61d489c..1a855a6 100644 --- a/drivers/clk/meson/g12a-ao.c +++ b/drivers/clk/meson/g12a-ao.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <common.h> #include <log.h> #include <asm/io.h> #include <clk-uclass.h> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 5d7faaa..e4fed8d 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -5,6 +5,7 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ +#include <common.h> #include <log.h> #include <asm/arch/clock-g12a.h> #include <asm/io.h> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 72ad4fd..e379540 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -5,6 +5,7 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ +#include <common.h> #include <log.h> #include <asm/arch/clock-gx.h> #include <asm/io.h> diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 0a82777..08f8bfc 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c index 5e8fb99..5739fd6 100644 --- a/drivers/clk/microchip/mpfs_clk_cfg.c +++ b/drivers/clk/microchip/mpfs_clk_cfg.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <asm/io.h> diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c index d0e7b1f..f37c0d8 100644 --- a/drivers/clk/microchip/mpfs_clk_msspll.c +++ b/drivers/clk/microchip/mpfs_clk_msspll.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2022 Microchip Technology Inc. */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <asm/io.h> diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c index 41c6df4..ddeccb9 100644 --- a/drivers/clk/microchip/mpfs_clk_periph.c +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <asm/io.h> diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index a29ad0d..cc73445 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include <common.h> #include <clk-uclass.h> #include <clock_legacy.h> #include <command.h> diff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c index 2e263fb..4d3ac84 100644 --- a/drivers/clk/mtmips/clk-mt7628.c +++ b/drivers/clk/mtmips/clk-mt7628.c @@ -5,6 +5,7 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-bindings/clock/mt7628-clk.h> diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 3033039..f5c9bd7 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -8,6 +8,7 @@ * Gregory CLEMENT <gregory.clement@free-electrons.com> */ +#include <common.h> #include <malloc.h> #include <clk-uclass.h> #include <clk.h> diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c index c1bab84..846a73c 100644 --- a/drivers/clk/mvebu/armada-37xx-tbg.c +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -8,6 +8,7 @@ * Gregory CLEMENT <gregory.clement@free-electrons.com> */ +#include <common.h> #include <clk-uclass.h> #include <clk.h> #include <dm.h> diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c index 513112c..678fdd5 100644 --- a/drivers/clk/owl/clk_owl.c +++ b/drivers/clk/owl/clk_owl.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ +#include <common.h> #include <dm.h> #include "clk_owl.h" #include <asm/io.h> diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 41fe4d8..d3b63b9 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -7,6 +7,7 @@ * Based on Little Kernel driver, simplified */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index c77d691..479f977 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -7,6 +7,7 @@ * Based on Little Kernel driver, simplified */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 0e6d93b..72f235e 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -9,6 +9,7 @@ */ #include <clk-uclass.h> +#include <common.h> #include <dm.h> #include <errno.h> #include <dt-bindings/clock/qcom,gcc-ipq4019.h> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 3a9cf2a..05e5ab7 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -12,6 +12,7 @@ * Based on Little Kernel driver, simplified */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dm/device-internal.h> diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 70a1f64..8a897a5 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -5,6 +5,7 @@ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index f41f8c9..782df7d 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -8,6 +8,7 @@ * Based on Little Kernel driver, simplified */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <linux/delay.h> diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 44c6f14..66f8bb1 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd */ + #include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index d7825c6..2875c15 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 274428f..6238b14 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c index f7dea78..f83335d 100644 --- a/drivers/clk/rockchip/clk_rk3066.c +++ b/drivers/clk/rockchip/clk_rk3066.c @@ -5,6 +5,7 @@ */ #include <bitfield.h> +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-structs.h> diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index a072855..182754e 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index f569a10..f98b46a 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -4,6 +4,7 @@ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-structs.h> diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 9b71fd8..9371c4f 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 432a792..0b7eefa 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <div64.h> diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index e73bb67..8616483 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2017-2019 Rockchip Electronics Co., Ltd */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 4b94d63..314b903 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> @@ -705,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case PCLK_HDMIPHY: rate = rk3328_hdmiphy_get_clk(priv->cru); break; + case SCLK_USB3OTG_REF: + rate = OSC_HZ; + break; default: return -ENOENT; } @@ -779,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case PCLK_DDR: case ACLK_GMAC: case PCLK_GMAC: + case SCLK_USB3OTG_REF: case SCLK_USB3OTG_SUSPEND: case USB480M: return 0; diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index d894398..1c5dfaa 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -5,6 +5,7 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-structs.h> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index cc414c3..67b2c05 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -4,6 +4,7 @@ * (C) 2017 Theobroma Systems Design und Consulting GmbH */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dt-structs.h> @@ -925,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz) return rk3399_saradc_get_clk(cru); } +static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru) +{ + if (readl(&cru->clksel_con[18]) & BIT(10)) + return 100 * MHz; + else + return OSC_HZ; +} + +static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz) +{ + if (hz == 100 * MHz) + rk_setreg(&cru->clksel_con[18], BIT(10)); + else if (hz == OSC_HZ) + rk_clrreg(&cru->clksel_con[18], BIT(10)); + else + return -EINVAL; + + return rk3399_pciephy_get_clk(cru); +} + static ulong rk3399_clk_get_rate(struct clk *clk) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); @@ -955,7 +976,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: - return 24000000; + case SCLK_USB3OTG0_REF: + case SCLK_USB3OTG1_REF: + return OSC_HZ; case PCLK_HDMI_CTRL: break; case DCLK_VOP0: @@ -966,10 +989,14 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3399_saradc_get_clk(priv->cru); break; + case SCLK_PCIEPHY_REF: + rate = rk3399_pciephy_get_clk(priv->cru); + break; case ACLK_VIO: case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR: + case ACLK_VDU: break; case PCLK_ALIVE: case PCLK_WDT: @@ -1048,7 +1075,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0; - case SCLK_DDRCLK: + case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS: @@ -1056,10 +1083,14 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3399_saradc_set_clk(priv->cru, rate); break; + case SCLK_PCIEPHY_REF: + ret = rk3399_pciephy_set_clk(priv->cru, rate); + break; case ACLK_VIO: case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR: + case ACLK_VDU: return 0; default: log_debug("Unknown clock %lu\n", clk->id); @@ -1105,12 +1136,39 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, return -EINVAL; } +static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk, + struct clk *parent) +{ + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); + const char *clock_output_name; + int ret; + + if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) { + rk_setreg(&priv->cru->clksel_con[18], BIT(10)); + return 0; + } + + ret = dev_read_string_index(parent->dev, "clock-output-names", + parent->id, &clock_output_name); + if (ret < 0) + return -ENODATA; + + if (!strcmp(clock_output_name, "xin24m")) { + rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + return 0; + } + + return -EINVAL; +} + static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) { switch (clk->id) { case SCLK_RMII_SRC: return rk3399_gmac_set_parent(clk, parent); + case SCLK_PCIEPHY_REF: + return rk3399_pciephy_set_parent(clk, parent); } debug("%s: unsupported clk %ld\n", __func__, clk->id); @@ -1201,7 +1259,8 @@ static int rk3399_clk_enable(struct clk *clk) rk_clrreg(&priv->cru->clkgate_con[13], BIT(7)); break; case SCLK_PCIEPHY_REF: - rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + if (readl(&priv->cru->clksel_con[18]) & BIT(10)) + rk_clrreg(&priv->cru->clkgate_con[12], BIT(6)); break; default: debug("%s: unsupported clk %ld\n", __func__, clk->id); @@ -1295,7 +1354,8 @@ static int rk3399_clk_disable(struct clk *clk) rk_setreg(&priv->cru->clkgate_con[13], BIT(7)); break; case SCLK_PCIEPHY_REF: - rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + if (readl(&priv->cru->clksel_con[18]) & BIT(10)) + rk_setreg(&priv->cru->clkgate_con[12], BIT(6)); break; default: debug("%s: unsupported clk %ld\n", __func__, clk->id); diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 3556350..24eeca8 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -4,6 +4,7 @@ * Author: Elaine Zhang <zhangqing@rock-chips.com> */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index ceae08a..4c611a3 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -4,6 +4,7 @@ * Author: Elaine Zhang <zhangqing@rock-chips.com> */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 75202a6..fc442f7 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -4,6 +4,7 @@ * Author: Andy Yan <andy.yan@rock-chips.com> */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index aeeea95..cfdfcbd 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -5,6 +5,7 @@ * Author: Finley Xiao <finley.xiao@rock-chips.com> */ +#include <common.h> #include <bitfield.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 5ea8606..c8fb600 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -22,6 +22,7 @@ * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 */ +#include <common.h> #include <clk-uclass.h> #include <clk.h> #include <dm.h> diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 5810358..1568a1f 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -6,6 +6,7 @@ * Xingyu Wu <xingyu.wu@starfivetech.com> */ +#include <common.h> #include <asm/io.h> #include <malloc.h> #include <clk-uclass.h> diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 191da75..a386948 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -6,6 +6,7 @@ * Xingyu Wu <xingyu.wu@starfivetech.com> */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index cad07cc..37e996e 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index fceb3c4..d68c75e 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index a554eda..d440c28 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 204ac17..6f000c8 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include <common.h> #include <clk-uclass.h> #include <div64.h> #include <dm.h> diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 362dba1..5174ae5 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_CLK #include <clk-uclass.h> +#include <common.h> #include <dm.h> #include <log.h> #include <asm/io.h> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 19fe248..f27306f 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index f771369..16ac589 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index fdee434..45d5ba7 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 04f76a7..6ca8000 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index f1b01d2..fd26cd4 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 6751af8..c5834f4 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index d8621a3..760d98c 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c index b990a11..9dae761 100644 --- a/drivers/clk/sunxi/clk_d1.c +++ b/drivers/clk/sunxi/clk_d1.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c index e229569..7b4c3ce 100644 --- a/drivers/clk/sunxi/clk_f1c100s.c +++ b/drivers/clk/sunxi/clk_f1c100s.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 George Hilliard <thirtythreeforty@gmail.com>. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index ce55cae..32bc95f 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 1b7bd9d..071fd58 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index b1e999e..113dcff 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 721debd..0fef6f3 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 2ef4f45..1782cff 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 85410e2..6524c13 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <errno.h> diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index 1d61f8d..c5214b9 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c index ec52326..5a98a3f 100644 --- a/drivers/clk/tegra/tegra186-clk.c +++ b/drivers/clk/tegra/tegra186-clk.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <log.h> diff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c index 1b0b981..3cf279d 100644 --- a/drivers/clk/ti/clk-am3-dpll-x2.c +++ b/drivers/clk/ti/clk-am3-dpll-x2.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/dpll.c */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dm/device_compat.h> diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c index 21ec01f..398a011 100644 --- a/drivers/clk/ti/clk-am3-dpll.c +++ b/drivers/clk/ti/clk-am3-dpll.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/dpll.c */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <div64.h> diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c index c5c97dc..8926e57 100644 --- a/drivers/clk/ti/clk-ctrl.c +++ b/drivers/clk/ti/clk-ctrl.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> */ +#include <common.h> #include <dm.h> #include <dm/device_compat.h> #include <clk-uclass.h> diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c index 40a742d..15941f1 100644 --- a/drivers/clk/ti/clk-divider.c +++ b/drivers/clk/ti/clk-divider.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/divider.c */ +#include <common.h> #include <clk.h> #include <clk-uclass.h> #include <div64.h> diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c index 873ceb8..eb15f62 100644 --- a/drivers/clk/ti/clk-gate.c +++ b/drivers/clk/ti/clk-gate.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/gate.c */ +#include <common.h> #include <dm.h> #include <dm/device_compat.h> #include <clk-uclass.h> diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index b3a1b4c..8323e6e 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -6,6 +6,7 @@ * Tero Kristo <t-kristo@ti.com> */ +#include <common.h> #include <asm/io.h> #include <dm.h> #include <div64.h> diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 41e5022..7aa162c 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -6,6 +6,7 @@ * Tero Kristo <t-kristo@ti.com> */ +#include <common.h> #include <dm.h> #include <errno.h> #include <soc.h> diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c index db53934..215241b 100644 --- a/drivers/clk/ti/clk-mux.c +++ b/drivers/clk/ti/clk-mux.c @@ -7,6 +7,7 @@ * Based on Linux kernel drivers/clk/ti/mux.c */ +#include <common.h> #include <dm.h> #include <dm/device_compat.h> #include <clk-uclass.h> diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c index e374bd3..9e5760d 100644 --- a/drivers/clk/ti/clk-sci.c +++ b/drivers/clk/ti/clk-sci.c @@ -8,6 +8,7 @@ * Loosely based on Linux kernel sci-clk.c... */ +#include <common.h> #include <dm.h> #include <errno.h> #include <clk-uclass.h> diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 28cd151..6e5cc90 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> */ +#include <common.h> #include <dm.h> #include <fdtdec.h> #include <regmap.h> diff --git a/drivers/clk/ti/omap4-cm.c b/drivers/clk/ti/omap4-cm.c index a30ce9d..3cdc9b2 100644 --- a/drivers/clk/ti/omap4-cm.c +++ b/drivers/clk/ti/omap4-cm.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> */ +#include <common.h> #include <dm.h> #include <dm/lists.h> diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 33369c9..c31e596 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ +#include <common.h> #include <clk-uclass.h> #include <dm.h> #include <dm/device_compat.h> |