diff options
Diffstat (limited to 'arch')
30 files changed, 129 insertions, 61 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index e619144..1b35fda 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -94,6 +94,7 @@ config NIOS2 bool "Nios II architecture" select CPU select DM + imply DM_EVENT select OF_CONTROL select SUPPORT_OF_CONTROL imply CMD_DM @@ -113,6 +114,7 @@ config RISCV select DM imply DM_SERIAL imply DM_ETH + imply DM_EVENT imply DM_MMC imply DM_SPI imply DM_SPI_FLASH @@ -238,6 +240,7 @@ config X86 imply CMD_SF_TEST imply CMD_ZBOOT imply DM_ETH + imply DM_EVENT imply DM_GPIO imply DM_KEYBOARD imply DM_MMC diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8c7f317..a6f2e7a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -774,6 +774,7 @@ config ARCH_OMAP2PLUS select SUPPORT_SPL imply TI_SYSC if DM && OF_CONTROL imply FIT + imply DM_EVENT config ARCH_MESON bool "Amlogic Meson" @@ -818,6 +819,7 @@ config ARCH_IMX8 select MACH_IMX select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK + imply DM_EVENT config ARCH_IMX8M bool "NXP i.MX8M platform" @@ -831,6 +833,7 @@ config ARCH_IMX8M select DM select SUPPORT_SPL imply CMD_DM + imply DM_EVENT config ARCH_IMX8ULP bool "NXP i.MX8ULP platform" @@ -841,6 +844,7 @@ config ARCH_IMX8ULP select SUPPORT_SPL select GPIO_EXTRA_HEADER imply CMD_DM + imply DM_EVENT config ARCH_IMXRT bool "NXP i.MXRT platform" diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 2eeef3c..f1e4e26 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -27,6 +27,37 @@ config ARMV7_BOOT_SEC_DEFAULT This can be overridden at run-time by setting the bootm_boot_mode env. variable to "sec" or "nonsec". +config HAS_ARMV7_SECURE_BASE + bool "Enable support for a ahardware secure memory area" + default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \ + || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124 + +config ARMV7_SECURE_BASE + hex "Base address for secure mode memory" + depends on HAS_ARMV7_SECURE_BASE + default 0xfff00000 if TEGRA124 + default 0x2ffc0000 if ARCH_STM32MP + default 0x2f000000 if ARCH_MX7ULP + default 0x10010000 if ARCH_LS1021A + default 0x00900000 if ARCH_MX7 + default 0x00044000 if MACH_SUN8I + default 0x00020000 if MACH_SUN6I || MACH_SUN7I + +config ARMV7_SECURE_RESERVE_SIZE + hex + depends on TEGRA124 && HAS_ARMV7_SECURE_BASE + default 0x100000 + help + Reserve top 1M for secure RAM + +config ARMV7_SECURE_MAX_SIZE + hex + depends on ARMV7_SECURE_BASE && ARCH_STM32MP || MACH_SUN6I \ + || MACH_SUN7I || MACH_SUN8I + default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3 + default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3 + default 0x10000 + config ARMV7_VIRT bool "Enable support for hardware virtualization" if EXPERT depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9967376..8d29393 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -31,6 +31,12 @@ config ARMV8_SET_SMPEN it can be safely enabled when EL2/EL3 initialized SMPEN bit or when CPU implementation doesn't include that register. +config ARMV8_SWITCH_TO_EL1 + bool + help + In some circumstances we need to switch to running in EL1. In + that case, select this option from your target Kconfig entry. + config ARMV8_SPIN_TABLE bool "Support spin-table enable method" depends on ARMV8_MULTIENTRY && OF_LIBFDT diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index ee5cc47..359f8c7 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -8,6 +8,7 @@ #include <cpu.h> #include <cpu_func.h> #include <dm.h> +#include <event.h> #include <init.h> #include <log.h> #include <asm/cache.h> @@ -66,7 +67,7 @@ int arch_cpu_init(void) return 0; } -int arch_cpu_init_dm(void) +static int imx8_init_mu(void *ctx, struct event *event) { struct udevice *devp; int node, ret; @@ -88,6 +89,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu); int print_bootinfo(void) { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 1a5a391..838f0a3 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -7,6 +7,7 @@ #include <common.h> #include <cpu_func.h> +#include <event.h> #include <init.h> #include <log.h> #include <asm/arch/imx-regs.h> @@ -494,7 +495,7 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog3->wmcr); } -int arch_cpu_init_dm(void) +static int imx8m_check_clock(void *ctx, struct event *event) { struct udevice *dev; int ret; @@ -511,6 +512,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); int arch_cpu_init(void) { diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 934b0ef..e6d417e 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -11,6 +11,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/global_data.h> #include <efi_loader.h> +#include <event.h> #include <spl.h> #include <asm/arch/rdc.h> #include <asm/arch/s400_api.h> @@ -569,7 +570,7 @@ int arch_cpu_init(void) return 0; } -int arch_cpu_init_dm(void) +static int imx8ulp_check_mu(void *ctx, struct event *event) { struct udevice *devp; int node, ret; @@ -584,6 +585,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu); #if defined(CONFIG_SPL_BUILD) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 681f649..fb4e5af 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -36,14 +36,6 @@ #define CONFIG_DM_SEQ_ALIAS 1 /* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ARP_TIMEOUT 200 -#define CONFIG_NET_RETRY_COUNT 50 -#endif /* CONFIG_CMD_NET */ - -/* * I2C related stuff */ #ifdef CONFIG_CMD_I2C diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index c446676..bcc907c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -11,6 +11,7 @@ #include <dm.h> #include <debug_uart.h> #include <errno.h> +#include <event.h> #include <init.h> #include <net.h> #include <ns16550.h> @@ -596,7 +597,7 @@ void board_init_f(ulong dummy) #endif -int arch_cpu_init_dm(void) +static int am33xx_dm_post_init(void *ctx, struct event *event) { hw_data_init(); #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) @@ -604,3 +605,4 @@ int arch_cpu_init_dm(void) #endif return 0; } +EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init); diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 3da50f9..c4a8eab 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -12,6 +12,7 @@ */ #include <common.h> #include <debug_uart.h> +#include <event.h> #include <fdtdec.h> #include <init.h> #include <spl.h> @@ -239,11 +240,13 @@ void board_init_f(ulong dummy) } #endif -int arch_cpu_init_dm(void) +static int omap2_system_init(void *ctx, struct event *event) { early_system_init(); + return 0; } +EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init); /* * Routine: wait_for_command_complete diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 205fe3c..2abc00e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -608,16 +608,8 @@ config SYS_CLK_FREQ default 1008000000 if MACH_SUN50I_H616 config SYS_CONFIG_NAME - default "suniv" if MACH_SUNIV - default "sun4i" if MACH_SUN4I - default "sun5i" if MACH_SUN5I - default "sun6i" if MACH_SUN6I - default "sun7i" if MACH_SUN7I - default "sun8i" if MACH_SUN8I - default "sun9i" if MACH_SUN9I - default "sun50i" if MACH_SUN50I - default "sun50i" if MACH_SUN50I_H6 - default "sun50i" if MACH_SUN50I_H616 + default "sun50i" if MACH_SUN50I || MACH_SUN50I_H6 || MACH_SUN50I_H616 + default "sunxi-common" config SYS_BOARD default "sunxi" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 28234aa..06cae68 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -130,6 +130,7 @@ config MACH_PIC32 config TARGET_BOSTON bool "Support Boston" select DM + imply DM_EVENT select DM_SERIAL select MIPS_CM select SYS_CACHE_SHIFT_6 diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index eac2fe5..de449e3 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -7,6 +7,7 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <event.h> #include <init.h> #include <malloc.h> #include <asm/global_data.h> @@ -95,12 +96,13 @@ static void prefetch_init(void) } /* arch specific CPU init after DM */ -int arch_cpu_init_dm(void) +static int pic32_flash_prefetch(void *ctx, struct event *event) { /* flash prefetch */ prefetch_init(); return 0; } +EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch); /* Un-gate DDR2 modules (gated by default) */ static void ddr2_pmd_ungate(void) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index b55c8fb..4dd9c10 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -10,6 +10,7 @@ #include <cpu_func.h> #include <dm.h> #include <errno.h> +#include <event.h> #include <init.h> #include <irq_func.h> #include <asm/cache.h> @@ -63,7 +64,7 @@ static void copy_exception_trampoline(void) } #endif -int arch_cpu_init_dm(void) +static int nios_cpu_setup(void *ctx, struct event *event) { struct udevice *dev; int ret; @@ -79,6 +80,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup); static int altera_nios2_get_desc(const struct udevice *dev, char *buf, int size) diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 3393ad5..33b2151 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -51,9 +51,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) REVID_MAJOR(spridr) >= 2) fdt_fixup_crypto_node(blob, 0x0204); -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ - defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) #ifdef CONFIG_ARCH_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 @@ -66,7 +63,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) nodeoffset = fdt_path_offset(blob, "/aliases"); if (nodeoffset >= 0) { -#if defined(CONFIG_HAS_ETH0) prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); if (prop) { u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 }; @@ -78,8 +74,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); } -#endif -#if defined(CONFIG_HAS_ETH1) prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); if (prop) { u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 }; @@ -91,11 +85,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); } -#endif } } #endif -#endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", (bd->bi_busfreq / 4), 1); diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index a978eea..b06416a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -354,6 +354,7 @@ config ARCH_MPC8560 config ARCH_P1010 bool + select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL select BTB select FSL_LAW select SYS_CACHE_SHIFT_5 @@ -878,6 +879,18 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config A003399_NOR_WORKAROUND + bool + help + Enables a workaround for IFC erratum A003399. It is only required + during NOR boot. + +config A008044_WORKAROUND + bool + help + Enables a workaround for T1040/T1042 erratum A008044. It is only + required during NAND boot and valid for Rev 1.0 SoC revision + config SYS_FSL_ERRATUM_A004468 bool @@ -960,6 +973,7 @@ config SYS_FSL_ERRATUM_A007907 config SYS_FSL_ERRATUM_A008044 bool + select A008044_WORKAROUND if MTD_RAW_NAND config SYS_FSL_ERRATUM_CPC_A002 bool diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index b1b002c..84eb8b4 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -456,18 +456,18 @@ void setup_mp(void) flush_cache(bootpg, 4096); /* look for the tlb covering the reset page, there better be one */ - i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); + i = find_tlb_idx((void *)BPTR_VIRT_ADDR, 1); /* we found a match */ if (i != -1) { /* map reset page to bootpg so we can copy code there */ disable_tlb(i); - set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ + set_tlb(1, BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ - memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); + memcpy((void *)BPTR_VIRT_ADDR, (void *)fixup, 4096); plat_mp_up(bootpg_map, pagesize); } else { diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 3541371..059ffe1 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -31,9 +31,7 @@ * Freescale's default e500 reset page. */ #if (defined(CONFIG_E500) && defined(CONFIG_MP)) -#ifndef CONFIG_BPTR_VIRT_ADDR -#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 -#endif +#define BPTR_VIRT_ADDR 0xfffff000 #endif /* Since so many PPC SOCs have a semi-common LBC, define this here */ diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 8d90c5e..3ffcbbd 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -7,9 +7,11 @@ #include <cpu.h> #include <dm.h> #include <dm/lists.h> +#include <event.h> #include <init.h> #include <log.h> #include <asm/encoding.h> +#include <asm/system.h> #include <dm/uclass-internal.h> #include <linux/bitops.h> @@ -81,7 +83,7 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) } #endif -int arch_cpu_init_dm(void) +int riscv_cpu_setup(void *ctx, struct event *event) { int ret; @@ -133,6 +135,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup); int arch_early_init_r(void) { diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index a340475..9d8e43e 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -7,6 +7,8 @@ #ifndef __ASM_RISCV_SYSTEM_H #define __ASM_RISCV_SYSTEM_H +struct event; + /* * Interrupt configuring macros. * @@ -14,4 +16,7 @@ * */ +/* Hook to set up the CPU (called from SPL too) */ +int riscv_cpu_setup(void *ctx, struct event *event); + #endif /* __ASM_RISCV_SYSTEM_H */ diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 8baee07..f4d3b67 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -11,6 +11,7 @@ #include <spl.h> #include <asm/global_data.h> #include <asm/smp.h> +#include <asm/system.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +28,7 @@ __weak void board_init_f(ulong dummy) if (ret) panic("spl_early_init() failed: %d\n", ret); - arch_cpu_init_dm(); + riscv_cpu_setup(NULL, NULL); preloader_console_init(); diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 13b0731..0f5a873 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -4,14 +4,14 @@ */ #include <common.h> +#include <cli.h> #include <command.h> -#include <dm/root.h> #include <efi_loader.h> #include <errno.h> +#include <event.h> #include <init.h> #include <log.h> #include <os.h> -#include <cli.h> #include <sort.h> #include <asm/getopt.h> #include <asm/global_data.h> @@ -19,6 +19,7 @@ #include <asm/malloc.h> #include <asm/sections.h> #include <asm/state.h> +#include <dm/root.h> #include <linux/ctype.h> DECLARE_GLOBAL_DATA_PTR; @@ -119,10 +120,11 @@ int sandbox_early_getopt_check(void) os_exit(0); } -int misc_init_f(void) +static int sandbox_misc_init_f(void *ctx, struct event *event) { return sandbox_early_getopt_check(); } +EVENT_SPY(EVT_MISC_INIT_F, sandbox_misc_init_f); static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg) { diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 309a50a..68bf40b 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -8,6 +8,7 @@ #include <common.h> #include <cpu.h> #include <dm.h> +#include <event.h> #include <init.h> #include <log.h> #include <pci.h> @@ -44,7 +45,7 @@ static void hsuart_clock_set(void *base) * Configure the internal clock of both SIO HS-UARTs, if they are enabled * via FSP */ -int arch_cpu_init_dm(void) +static int baytrail_uart_init(void *ctx, struct event *event) { struct udevice *dev; void *base; @@ -63,6 +64,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init); static void set_max_freq(void) { diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 3832a97..2adcf4b 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -8,6 +8,7 @@ #include <common.h> #include <dm.h> #include <cpu.h> +#include <event.h> #include <init.h> #include <log.h> #include <asm/cpu.h> @@ -24,7 +25,7 @@ #include <asm/arch/pch.h> #include <asm/arch/rcb.h> -int arch_cpu_init_dm(void) +static int broadwell_init_cpu(void *ctx, struct event *event) { struct udevice *dev; int ret; @@ -41,6 +42,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu); void set_max_freq(void) { diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index a02f4f9..cffc5d5 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -14,6 +14,7 @@ #include <cpu_func.h> #include <dm.h> #include <errno.h> +#include <event.h> #include <fdtdec.h> #include <init.h> #include <log.h> @@ -53,7 +54,7 @@ int arch_cpu_init(void) return x86_cpu_init_f(); } -int arch_cpu_init_dm(void) +static int ivybridge_cpu_init(void *ctx, struct event *ev) { struct pci_controller *hose; struct udevice *bus, *dev; @@ -85,6 +86,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init); #define PCH_EHCI0_TEMP_BAR0 0xe8000000 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 30b4711..e016fae 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -5,6 +5,7 @@ #include <common.h> #include <cpu_func.h> +#include <event.h> #include <init.h> #include <mmc.h> #include <asm/cache.h> @@ -247,7 +248,7 @@ int arch_cpu_init(void) return 0; } -int arch_cpu_init_dm(void) +static int quark_init_pcie(void *ctx, struct event *event) { /* * Initialize PCIe controller @@ -262,6 +263,7 @@ int arch_cpu_init_dm(void) return 0; } +EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie); int checkcpu(void) { diff --git a/arch/x86/include/asm/fsp2/fsp_api.h b/arch/x86/include/asm/fsp2/fsp_api.h index dccbfa4..ca3f684 100644 --- a/arch/x86/include/asm/fsp2/fsp_api.h +++ b/arch/x86/include/asm/fsp2/fsp_api.h @@ -60,4 +60,12 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash); typedef asmlinkage int (*fsp_silicon_init_func)(struct fsps_upd *params); +/** + * fsp_setup_pinctrl() - Set up the pinctrl for FSP + * + * @ctx: Event context (not used) + * @event: Event information (not used) + */ +int fsp_setup_pinctrl(void *ctx, struct event *event); + #endif diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index 5afdce1..b15926e 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -9,6 +9,7 @@ #include <bootstage.h> #include <cbfs.h> #include <dm.h> +#include <event.h> #include <init.h> #include <log.h> #include <spi.h> @@ -18,7 +19,7 @@ #include <dm/uclass-internal.h> #include <asm/fsp2/fsp_internal.h> -int arch_cpu_init_dm(void) +int fsp_setup_pinctrl(void *ctx, struct event *event) { struct udevice *dev; ofnode node; @@ -41,6 +42,7 @@ int arch_cpu_init_dm(void) return ret; } +EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl); #if !defined(CONFIG_TPL_BUILD) binman_sym_declare(ulong, intel_fsp_m, image_pos); diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index b18c1cd..2d50c62 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -17,6 +17,7 @@ #include <syscon.h> #include <asm/cpu.h> #include <asm/cpu_common.h> +#include <asm/fsp2/fsp_api.h> #include <asm/global_data.h> #include <asm/mrccache.h> #include <asm/mtrr.h> @@ -27,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; -__weak int arch_cpu_init_dm(void) +__weak int fsp_setup_pinctrl(void *ctx, struct event *event) { return 0; } @@ -89,7 +90,7 @@ static int x86_spl_init(void) return ret; } #ifndef CONFIG_TPL - ret = arch_cpu_init_dm(); + ret = fsp_setup_pinctrl(NULL, NULL); if (ret) { debug("%s: arch_cpu_init_dm() failed\n", __func__); return ret; diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 5b57e53..18b05b2 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -__weak int arch_cpu_init_dm(void) -{ - return 0; -} - static int x86_tpl_init(void) { int ret; @@ -44,11 +39,6 @@ static int x86_tpl_init(void) debug("%s: arch_cpu_init() failed\n", __func__); return ret; } - ret = arch_cpu_init_dm(); - if (ret) { - debug("%s: arch_cpu_init_dm() failed\n", __func__); - return ret; - } preloader_console_init(); return 0; |