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-rw-r--r--arch/sh/Kconfig4
-rw-r--r--arch/sh/cpu/sh3/Makefile12
-rw-r--r--arch/sh/cpu/sh3/config.mk12
-rw-r--r--arch/sh/cpu/sh3/cpu.c67
-rw-r--r--arch/sh/cpu/sh3/interrupts.c25
-rw-r--r--arch/sh/cpu/sh3/watchdog.c26
-rw-r--r--arch/sh/include/asm/cpu_sh3.h30
-rw-r--r--arch/sh/include/asm/cpu_sh7706.h50
-rw-r--r--arch/sh/include/asm/cpu_sh7710.h61
-rw-r--r--arch/sh/include/asm/cpu_sh7720.h206
-rw-r--r--arch/sh/include/asm/processor.h4
-rw-r--r--arch/sh/lib/Makefile1
-rw-r--r--arch/sh/lib/time.c5
13 files changed, 0 insertions, 503 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 60589b3..0ce74cf 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -1,9 +1,6 @@
menu "SuperH architecture"
depends on SH
-config CPU_SH3
- bool
-
config CPU_SH4
bool
@@ -82,7 +79,6 @@ config SYS_ARCH
default "sh"
config SYS_CPU
- default "sh3" if CPU_SH3
default "sh4" if CPU_SH4
source "arch/sh/lib/Kconfig"
diff --git a/arch/sh/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile
deleted file mode 100644
index 24aca92..0000000
--- a/arch/sh/cpu/sh3/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# (C) Copyright 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-
-obj-y = cpu.o interrupts.o watchdog.o
diff --git a/arch/sh/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk
deleted file mode 100644
index e13ee12..0000000
--- a/arch/sh/cpu/sh3/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# (C) Copyright 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-PLATFORM_CPPFLAGS += -m3
diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c
deleted file mode 100644
index 98121c7..0000000
--- a/arch/sh/cpu/sh3/cpu.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-
-int checkcpu(void)
-{
- puts("CPU: SH3\n");
- return 0;
-}
-
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- reset_cpu(0);
- return 0;
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh3/interrupts.c b/arch/sh/cpu/sh3/interrupts.c
deleted file mode 100644
index 144505a..0000000
--- a/arch/sh/cpu/sh3/interrupts.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-void enable_interrupts(void)
-{
-
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh3/watchdog.c b/arch/sh/cpu/sh3/watchdog.c
deleted file mode 100644
index 40bb33e..0000000
--- a/arch/sh/cpu/sh3/watchdog.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-
-int watchdog_init(void)
-{
- return 0;
-}
-
-void reset_cpu(unsigned long ignored)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
diff --git a/arch/sh/include/asm/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h
deleted file mode 100644
index a5d3ff7..0000000
--- a/arch/sh/include/asm/cpu_sh3.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#ifndef _ASM_CPU_SH3_H_
-#define _ASM_CPU_SH3_H_
-
-/* cache control */
-#define CCR_CACHE_STOP 0x00000008
-#define CCR_CACHE_ENABLE 0x00000005
-#define CCR_CACHE_ICI 0x00000008
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_OC_WAY_SHIFT 13
-#define CACHE_OC_NUM_ENTRIES 256
-#define CACHE_OC_ENTRY_SHIFT 4
-
-#if defined(CONFIG_CPU_SH7706)
-#include <asm/cpu_sh7706.h>
-#elif defined(CONFIG_CPU_SH7710)
-#include <asm/cpu_sh7710.h>
-#elif defined(CONFIG_CPU_SH7720)
-#include <asm/cpu_sh7720.h>
-#else
-#error "Unknown SH3 variant"
-#endif
-
-#endif /* _ASM_CPU_SH3_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h
deleted file mode 100644
index 8066ff7..0000000
--- a/arch/sh/include/asm/cpu_sh7706.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef _ASM_CPU_SH7706_H_
-#define _ASM_CPU_SH7706_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000D
-
-/* MMU and Cache control */
-#define MMUCR 0xFFFFFFE0
-#define CCR 0xFFFFFFEC
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-#define FRQCR 0xffffff80
-#define BCR1 0xffffff60
-#define BCR2 0xffffff62
-#define WCR1 0xffffff64
-#define WCR2 0xffffff66
-#define MCR 0xffffff68
-
-/* SDRAM controller */
-#define DCR 0xffffff6a
-#define RTCSR 0xffffff6e
-#define RTCNT 0xffffff70
-#define RTCOR 0xffffff72
-#define RFCR 0xffffff74
-#define SDMR 0xFFFFD000
-#define CS3_R 0xFFFFE460
-
-/* SCIF */
-#define SCSMR_2 0xA4000150
-#define SCIF0_BASE SCSMR_2
-
-/* Timer */
-#define TMU_BASE 0xFFFFFE90
-
-/* On chip oscillator circuits */
-#define WTCNT 0xFFFFFF84
-#define WTCSR 0xFFFFFF86
-
-#endif /* _ASM_CPU_SH7706_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7710.h b/arch/sh/include/asm/cpu_sh7710.h
deleted file mode 100644
index e4ecef7..0000000
--- a/arch/sh/include/asm/cpu_sh7710.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef _ASM_CPU_SH7710_H_
-#define _ASM_CPU_SH7710_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000D
-
-/* MMU and Cache control */
-#define MMUCR 0xFFFFFFE0
-#define CCR 0xFFFFFFEC
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-#define CMNCR 0xA4FD0000
-#define CS0BCR 0xA4FD0004
-#define CS2BCR 0xA4FD0008
-#define CS3BCR 0xA4FD000C
-#define CS4BCR 0xA4FD0010
-#define CS5ABCR 0xA4FD0014
-#define CS5BBCR 0xA4FD0018
-#define CS6ABCR 0xA4FD001C
-#define CS6BBCR 0xA4FD0020
-#define CS0WCR 0xA4FD0024
-#define CS2WCR 0xA4FD0028
-#define CS3WCR 0xA4FD002C
-#define CS4WCR 0xA4FD0030
-#define CS5AWCR 0xA4FD0034
-#define CS5BWCR 0xA4FD0038
-#define CS6AWCR 0xA4FD003C
-#define CS6BWCR 0xA4FD0040
-
-/* SDRAM controller */
-#define SDCR 0xA4FD0044
-#define RTCSR 0xA4FD0048
-#define RTCNT 0xA4FD004C
-#define RTCOR 0xA4FD0050
-
-/* SCIF */
-#define SCSMR_0 0xA4400000
-#define SCIF0_BASE SCSMR_0
-#define SCSMR_0 0xA4410000
-#define SCIF1_BASE SCSMR_1
-
-/* Timer */
-#define TMU_BASE 0xA412FE90
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7710_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h
deleted file mode 100644
index 5c361ac..0000000
--- a/arch/sh/include/asm/cpu_sh7720.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007 (C)
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright 2008 (C)
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * SH7720 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7720_H_
-#define _ASM_CPU_SH7720_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000B
-
-/* EXP */
-#define TRA 0xFFFFFFD0
-#define EXPEVT 0xFFFFFFD4
-#define INTEVT 0xFFFFFFD8
-
-/* MMU */
-#define MMUCR 0xFFFFFFE0
-#define PTEH 0xFFFFFFF0
-#define PTEL 0xFFFFFFF4
-#define TTB 0xFFFFFFF8
-
-/* CACHE */
-#define CCR 0xFFFFFFEC
-
-/* INTC */
-#define IPRF 0xA4080000
-#define IPRG 0xA4080002
-#define IPRH 0xA4080004
-#define IPRI 0xA4080006
-#define IPRJ 0xA4080008
-#define IRR5 0xA4080020
-#define IRR6 0xA4080022
-#define IRR7 0xA4080024
-#define IRR8 0xA4080026
-#define IRR9 0xA4080028
-#define IRR0 0xA4140004
-#define IRR1 0xA4140006
-#define IRR2 0xA4140008
-#define IRR3 0xA414000A
-#define IRR4 0xA414000C
-#define ICR1 0xA4140010
-#define ICR2 0xA4140012
-#define PINTER 0xA4140014
-#define IPRC 0xA4140016
-#define IPRD 0xA4140018
-#define IPRE 0xA414001A
-#define ICR0 0xA414FEE0
-#define IPRA 0xA414FEE2
-#define IPRB 0xA414FEE4
-
-/* BSC */
-#define BSC_BASE 0xA4FD0000
-#define CMNCR (BSC_BASE + 0x00)
-#define CS0BCR (BSC_BASE + 0x04)
-#define CS2BCR (BSC_BASE + 0x08)
-#define CS3BCR (BSC_BASE + 0x0C)
-#define CS4BCR (BSC_BASE + 0x10)
-#define CS5ABCR (BSC_BASE + 0x14)
-#define CS5BBCR (BSC_BASE + 0x18)
-#define CS6ABCR (BSC_BASE + 0x1C)
-#define CS6BBCR (BSC_BASE + 0x20)
-#define CS0WCR (BSC_BASE + 0x24)
-#define CS2WCR (BSC_BASE + 0x28)
-#define CS3WCR (BSC_BASE + 0x2C)
-#define CS4WCR (BSC_BASE + 0x30)
-#define CS5AWCR (BSC_BASE + 0x34)
-#define CS5BWCR (BSC_BASE + 0x38)
-#define CS6AWCR (BSC_BASE + 0x3C)
-#define CS6BWCR (BSC_BASE + 0x40)
-#define SDCR (BSC_BASE + 0x44)
-#define RTCSR (BSC_BASE + 0x48)
-#define RTCNR (BSC_BASE + 0x4C)
-#define RTCOR (BSC_BASE + 0x50)
-#define SDMR2 (BSC_BASE + 0x4000)
-#define SDMR3 (BSC_BASE + 0x5000)
-
-/* DMAC */
-
-/* CPG */
-#define UCLKCR 0xA40A0008
-#define FRQCR 0xA415FF80
-
-/* LOW POWER MODE */
-
-/* TMU */
-#define TMU_BASE 0xA412FE90
-
-/* TPU */
-#define TPU_BASE 0xA4480000
-#define TPU_TSTR (TPU_BASE + 0x00)
-#define TPU_TCR0 (TPU_BASE + 0x10)
-#define TPU_TMDR0 (TPU_BASE + 0x14)
-#define TPU_TIOR0 (TPU_BASE + 0x18)
-#define TPU_TIER0 (TPU_BASE + 0x1C)
-#define TPU_TSR0 (TPU_BASE + 0x20)
-#define TPU_TCNT0 (TPU_BASE + 0x24)
-#define TPU_TGRA0 (TPU_BASE + 0x28)
-#define TPU_TGRB0 (TPU_BASE + 0x2C)
-#define TPU_TGRC0 (TPU_BASE + 0x30)
-#define TPU_TGRD0 (TPU_BASE + 0x34)
-#define TPU_TCR1 (TPU_BASE + 0x50)
-#define TPU_TMDR1 (TPU_BASE + 0x54)
-#define TPU_TIOR1 (TPU_BASE + 0x58)
-#define TPU_TIER1 (TPU_BASE + 0x5C)
-#define TPU_TSR1 (TPU_BASE + 0x60)
-#define TPU_TCNT1 (TPU_BASE + 0x64)
-#define TPU_TGRA1 (TPU_BASE + 0x68)
-#define TPU_TGRB1 (TPU_BASE + 0x6C)
-#define TPU_TGRC1 (TPU_BASE + 0x70)
-#define TPU_TGRD1 (TPU_BASE + 0x74)
-#define TPU_TCR2 (TPU_BASE + 0x90)
-#define TPU_TMDR2 (TPU_BASE + 0x94)
-#define TPU_TIOR2 (TPU_BASE + 0x98)
-#define TPU_TIER2 (TPU_BASE + 0x9C)
-#define TPU_TSR2 (TPU_BASE + 0xB0)
-#define TPU_TCNT2 (TPU_BASE + 0xB4)
-#define TPU_TGRA2 (TPU_BASE + 0xB8)
-#define TPU_TGRB2 (TPU_BASE + 0xBC)
-#define TPU_TGRC2 (TPU_BASE + 0xC0)
-#define TPU_TGRD2 (TPU_BASE + 0xC4)
-#define TPU_TCR3 (TPU_BASE + 0xD0)
-#define TPU_TMDR3 (TPU_BASE + 0xD4)
-#define TPU_TIOR3 (TPU_BASE + 0xD8)
-#define TPU_TIER3 (TPU_BASE + 0xDC)
-#define TPU_TSR3 (TPU_BASE + 0xE0)
-#define TPU_TCNT3 (TPU_BASE + 0xE4)
-#define TPU_TGRA3 (TPU_BASE + 0xE8)
-#define TPU_TGRB3 (TPU_BASE + 0xEC)
-#define TPU_TGRC3 (TPU_BASE + 0xF0)
-#define TPU_TGRD3 (TPU_BASE + 0xF4)
-
-/* CMT */
-
-/* SIOF */
-
-/* SCIF */
-#define SCIF0_BASE 0xA4430000
-
-/* SIM */
-
-/* IrDA */
-
-/* IIC */
-
-/* LCDC */
-
-/* USBF */
-
-/* MMCIF */
-
-/* PFC */
-#define PFC_BASE 0xA4050100
-#define PACR (PFC_BASE + 0x00)
-#define PBCR (PFC_BASE + 0x02)
-#define PCCR (PFC_BASE + 0x04)
-#define PDCR (PFC_BASE + 0x06)
-#define PECR (PFC_BASE + 0x08)
-#define PFCR (PFC_BASE + 0x0A)
-#define PGCR (PFC_BASE + 0x0C)
-#define PHCR (PFC_BASE + 0x0E)
-#define PJCR (PFC_BASE + 0x10)
-#define PKCR (PFC_BASE + 0x12)
-#define PLCR (PFC_BASE + 0x14)
-#define PMCR (PFC_BASE + 0x16)
-#define PPCR (PFC_BASE + 0x18)
-#define PRCR (PFC_BASE + 0x1A)
-#define PSCR (PFC_BASE + 0x1C)
-#define PTCR (PFC_BASE + 0x1E)
-#define PUCR (PFC_BASE + 0x20)
-#define PVCR (PFC_BASE + 0x22)
-#define PSELA (PFC_BASE + 0x24)
-#define PSELB (PFC_BASE + 0x26)
-#define PSELC (PFC_BASE + 0x28)
-#define PSELD (PFC_BASE + 0x2A)
-
-/* I/O Port */
-#define PORT_BASE 0xA4050100
-#define PADR (PORT_BASE + 0x40)
-#define PBDR (PORT_BASE + 0x42)
-#define PCDR (PORT_BASE + 0x44)
-#define PDDR (PORT_BASE + 0x46)
-#define PEDR (PORT_BASE + 0x48)
-#define PFDR (PORT_BASE + 0x4A)
-#define PGDR (PORT_BASE + 0x4C)
-#define PHDR (PORT_BASE + 0x4E)
-#define PJDR (PORT_BASE + 0x50)
-#define PKDR (PORT_BASE + 0x52)
-#define PLDR (PORT_BASE + 0x54)
-#define PMDR (PORT_BASE + 0x56)
-#define PPDR (PORT_BASE + 0x58)
-#define PRDR (PORT_BASE + 0x5A)
-#define PSDR (PORT_BASE + 0x5C)
-#define PTDR (PORT_BASE + 0x5E)
-#define PUDR (PORT_BASE + 0x60)
-#define PVDR (PORT_BASE + 0x62)
-
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7720_H_ */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index bdc1da6..09de94a 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -1,8 +1,4 @@
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
-#if defined(CONFIG_CPU_SH3)
-# include <asm/cpu_sh3.h>
-#elif defined(CONFIG_CPU_SH4)
# include <asm/cpu_sh4.h>
#endif
-#endif
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index fbc4cc9..9618da1 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
udivsi3-y := udivsi3_i4i-Os.o
ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
-udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o
udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o
endif
udivsi3-y += udivsi3.o
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index fb317f9..51e1cc1 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -14,11 +14,6 @@
#include <asm/processor.h>
#include <asm/io.h>
-#if defined(CONFIG_CPU_SH3)
-#define TSTR 0x2
-#define TCR0 0xc
-#endif /* CONFIG_CPU_SH3 */
-
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
#define TSTR 0x4
#define TCR0 0x10
generated by cgit v1.1 at 2024-11-16 14:36:15 +0000