diff options
| -rw-r--r-- | doc/driver-model/i2c-howto.txt | 1 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/tsi108_i2c.c | 275 | ||||
| -rw-r--r-- | include/tsi108.h | 207 |
4 files changed, 0 insertions, 484 deletions
diff --git a/doc/driver-model/i2c-howto.txt b/doc/driver-model/i2c-howto.txt index 605d3ef..1b2c531 100644 --- a/doc/driver-model/i2c-howto.txt +++ b/doc/driver-model/i2c-howto.txt @@ -16,7 +16,6 @@ ones remain: sh_i2c sh_sh7734_i2c soft_i2c - tsi108_i2c zynq_i2c The deadline for this work is the end of June 2017. If no one steps diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 8bb3c18..4cf5c51 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o obj-$(CONFIG_I2C_MV) += mv_i2c.o -obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c deleted file mode 100644 index 208c090..0000000 --- a/drivers/i2c/tsi108_i2c.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 Tundra Semiconductor Corp. - * Author: Alex Bounine - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <config.h> -#include <common.h> - -#include <tsi108.h> - -#if defined(CONFIG_CMD_I2C) - -#define I2C_DELAY 100000 -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DPRINT(x) printf (x) -#else -#define DPRINT(x) -#endif - -/* All functions assume that Tsi108 I2C block is the only master on the bus */ -/* I2C read helper function */ - -void i2c_init(int speed, int slaveaddr) -{ - /* - * The TSI108 has a fixed I2C clock rate and doesn't support slave - * operation. This function only exists as a stub to fit into the - * U-Boot I2C API. - */ -} - -static int i2c_read_byte ( - uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ - uchar chip_addr,/* I2C device address on the bus */ - uint byte_addr, /* Byte address within I2C device */ - uchar * buffer /* pointer to data buffer */ - ) -{ - u32 temp; - u32 to_count = I2C_DELAY; - u32 op_status = TSI108_I2C_TIMEOUT_ERR; - u32 chan_offset = TSI108_I2C_OFFSET; - - DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", - i2c_chan, chip_addr, byte_addr)); - - if (0 != i2c_chan) - chan_offset = TSI108_I2C_SDRAM_OFFSET; - - /* Check if I2C operation is in progress */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | - I2C_CNTRL2_START))) { - /* Set device address and operation (read = 0) */ - temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | - ((chip_addr >> 3) & 0x0F); - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = - temp; - - /* Issue the read command - * (at this moment all other parameters are 0 - * (size = 1 byte, lane = 0) - */ - - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = - (I2C_CNTRL2_START); - - /* Wait until operation completed */ - do { - /* Read I2C operation status */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) { - if (0 == (temp & - (I2C_CNTRL2_I2C_CFGERR | - I2C_CNTRL2_I2C_TO_ERR)) - ) { - op_status = TSI108_I2C_SUCCESS; - - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + - chan_offset + - I2C_RD_DATA); - - *buffer = (u8) (temp & 0xFF); - } else { - /* report HW error */ - op_status = TSI108_I2C_IF_ERROR; - - DPRINT (("I2C HW error reported: 0x%02x\n", temp)); - } - - break; - } - } while (to_count--); - } else { - op_status = TSI108_I2C_IF_BUSY; - - DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); - } - - DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); - return op_status; -} - -/* - * I2C Read interface as defined in "include/i2c.h" : - * chip_addr: I2C chip address, range 0..127 - * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) - * NOTE: The bit 7 in the chip_addr serves as a channel select. - * This hack is for enabling "i2c sdram" command on Tsi108 boards - * without changes to common code. Used for I2C reads only. - * byte_addr: Memory or register address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Pointer to destination buffer for data to be read - * len: How many bytes to read - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_read (uchar chip_addr, uint byte_addr, int alen, - uchar * buffer, int len) -{ - u32 op_status = TSI108_I2C_PARAM_ERR; - u32 i2c_if = 0; - - /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/ - if (0xD0 == (chip_addr & ~0x07)) { - i2c_if = 1; - chip_addr &= 0x7F; - } - /* Check for valid I2C address */ - if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { - while (len--) { - op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++); - - if (TSI108_I2C_SUCCESS != op_status) { - DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); - - break; - } - } - } - - DPRINT (("I2C read() status: 0x%02x\n", op_status)); - return op_status; -} - -/* I2C write helper function */ - -static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ - uint byte_addr, /* Byte address within I2C device */ - uchar * buffer /* pointer to data buffer */ - ) -{ - u32 temp; - u32 to_count = I2C_DELAY; - u32 op_status = TSI108_I2C_TIMEOUT_ERR; - - /* Check if I2C operation is in progress */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { - /* Place data into the I2C Tx Register */ - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + - I2C_TX_DATA) = (u32) * buffer; - - /* Set device address and operation */ - temp = - I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | - ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + - I2C_CNTRL1) = temp; - - /* Issue the write command (at this moment all other parameters - * are 0 (size = 1 byte, lane = 0) - */ - - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + - I2C_CNTRL2) = (I2C_CNTRL2_START); - - op_status = TSI108_I2C_TIMEOUT_ERR; - - /* Wait until operation completed */ - do { - /* Read I2C operation status */ - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); - - if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { - if (0 == (temp & - (I2C_CNTRL2_I2C_CFGERR | - I2C_CNTRL2_I2C_TO_ERR))) { - op_status = TSI108_I2C_SUCCESS; - } else { - /* report detected HW error */ - op_status = TSI108_I2C_IF_ERROR; - - DPRINT (("I2C HW error reported: 0x%02x\n", temp)); - } - - break; - } - - } while (to_count--); - } else { - op_status = TSI108_I2C_IF_BUSY; - - DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); - } - - return op_status; -} - -/* - * I2C Write interface as defined in "include/i2c.h" : - * chip_addr: I2C chip address, range 0..127 - * byte_addr: Memory or register address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Pointer to data to be written - * len: How many bytes to write - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, - int len) -{ - u32 op_status = TSI108_I2C_PARAM_ERR; - - /* Check for valid I2C address */ - if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { - while (len--) { - op_status = - i2c_write_byte (chip_addr, byte_addr++, buffer++); - - if (TSI108_I2C_SUCCESS != op_status) { - DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); - - break; - } - } - } - - return op_status; -} - -/* - * I2C interface function as defined in "include/i2c.h". - * Probe the given I2C chip address by reading single byte from offset 0. - * Returns 0 if a chip responded, not 0 on failure. - */ - -int i2c_probe (uchar chip) -{ - u32 tmp; - - /* - * Try to read the first location of the chip. - * The Tsi108 HW doesn't support sending just the chip address - * and checkong for an <ACK> back. - */ - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -#endif diff --git a/include/tsi108.h b/include/tsi108.h deleted file mode 100644 index 8e246b8..0000000 --- a/include/tsi108.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/***************************************************************************** - * (C) Copyright 2003; Tundra Semiconductor Corp. - * (C) Copyright 2006; Freescale Semiconductor Corp. - *****************************************************************************/ - -/* - * FILENAME: tsi108.h - * - * Originator: Alex Bounine - * - * DESCRIPTION: - * Common definitions for the Tundra Tsi108 bridge chip - * - */ - -#ifndef _TSI108_H_ -#define _TSI108_H_ - -#define TSI108_HLP_REG_OFFSET (0x0000) -#define TSI108_PCI_REG_OFFSET (0x1000) -#define TSI108_CLK_REG_OFFSET (0x2000) -#define TSI108_PB_REG_OFFSET (0x3000) -#define TSI108_SD_REG_OFFSET (0x4000) -#define TSI108_MPIC_REG_OFFSET (0x7400) - -#define PB_ID (0x000) -#define PB_RSR (0x004) -#define PB_BUS_MS_SELECT (0x008) -#define PB_ISR (0x00C) -#define PB_ARB_CTRL (0x018) -#define PB_PVT_CTRL2 (0x034) -#define PB_SCR (0x400) -#define PB_ERRCS (0x404) -#define PB_AERR (0x408) -#define PB_REG_BAR (0x410) -#define PB_OCN_BAR1 (0x414) -#define PB_OCN_BAR2 (0x418) -#define PB_SDRAM_BAR1 (0x41C) -#define PB_SDRAM_BAR2 (0x420) -#define PB_MCR (0xC00) -#define PB_MCMD (0xC04) - -#define HLP_B0_ADDR (0x000) -#define HLP_B1_ADDR (0x010) -#define HLP_B2_ADDR (0x020) -#define HLP_B3_ADDR (0x030) - -#define HLP_B0_MASK (0x004) -#define HLP_B1_MASK (0x014) -#define HLP_B2_MASK (0x024) -#define HLP_B3_MASK (0x034) - -#define HLP_B0_CTRL0 (0x008) -#define HLP_B1_CTRL0 (0x018) -#define HLP_B2_CTRL0 (0x028) -#define HLP_B3_CTRL0 (0x038) - -#define HLP_B0_CTRL1 (0x00C) -#define HLP_B1_CTRL1 (0x01C) -#define HLP_B2_CTRL1 (0x02C) -#define HLP_B3_CTRL1 (0x03C) - -#define PCI_CSR (0x004) -#define PCI_P2O_BAR0 (0x010) -#define PCI_P2O_BAR0_UPPER (0x014) -#define PCI_P2O_BAR2 (0x018) -#define PCI_P2O_BAR2_UPPER (0x01C) -#define PCI_P2O_BAR3 (0x020) -#define PCI_P2O_BAR3_UPPER (0x024) - -#define PCI_MISC_CSR (0x040) -#define PCI_P2O_PAGE_SIZES (0x04C) - -#define PCI_PCIX_STAT (0x0F4) - -#define PCI_IRP_STAT (0x184) - -#define PCI_PFAB_BAR0 (0x204) -#define PCI_PFAB_BAR0_UPPER (0x208) -#define PCI_PFAB_IO (0x20C) -#define PCI_PFAB_IO_UPPER (0x210) - -#define PCI_PFAB_MEM32 (0x214) -#define PCI_PFAB_MEM32_REMAP (0x218) -#define PCI_PFAB_MEM32_MASK (0x21C) - -#define CG_PLL0_CTRL0 (0x210) -#define CG_PLL0_CTRL1 (0x214) -#define CG_PLL1_CTRL0 (0x220) -#define CG_PLL1_CTRL1 (0x224) -#define CG_PWRUP_STATUS (0x234) - -#define MPIC_CSR(n) (0x30C + (n * 0x40)) - -#define SD_CTRL (0x000) -#define SD_STATUS (0x004) -#define SD_TIMING (0x008) -#define SD_REFRESH (0x00C) -#define SD_INT_STATUS (0x010) -#define SD_INT_ENABLE (0x014) -#define SD_INT_SET (0x018) -#define SD_D0_CTRL (0x020) -#define SD_D1_CTRL (0x024) -#define SD_D0_BAR (0x028) -#define SD_D1_BAR (0x02C) -#define SD_ECC_CTRL (0x040) -#define SD_DLL_STATUS (0x250) - -#define TS_SD_CTRL_ENABLE (1 << 31) - -#define PB_ERRCS_ES (1 << 1) -#define PB_ISR_PBS_RD_ERR (1 << 8) -#define PCI_IRP_STAT_P_CSR (1 << 23) - -/* - * I2C : Register address offset definitions - */ -#define I2C_CNTRL1 (0x00000000) -#define I2C_CNTRL2 (0x00000004) -#define I2C_RD_DATA (0x00000008) -#define I2C_TX_DATA (0x0000000c) - -/* - * I2C : Register Bit Masks and Reset Values - * definitions for every register - */ - -/* I2C_CNTRL1 : Reset Value */ -#define I2C_CNTRL1_RESET_VALUE (0x0000000a) - -/* I2C_CNTRL1 : Register Bits Masks Definitions */ -#define I2C_CNTRL1_DEVCODE (0x0000000f) -#define I2C_CNTRL1_PAGE (0x00000700) -#define I2C_CNTRL1_BYTADDR (0x00ff0000) -#define I2C_CNTRL1_I2CWRITE (0x01000000) - -/* I2C_CNTRL1 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL1_RWMASK (0x01ff070f) - -/* I2C_CNTRL1 : Unused/Reserved bits Definition */ -#define I2C_CNTRL1_RESERVED (0xfe00f8f0) - -/* I2C_CNTRL2 : Reset Value */ -#define I2C_CNTRL2_RESET_VALUE (0x00000000) - -/* I2C_CNTRL2 : Register Bits Masks Definitions */ -#define I2C_CNTRL2_SIZE (0x00000003) -#define I2C_CNTRL2_LANE (0x0000000c) -#define I2C_CNTRL2_MULTIBYTE (0x00000010) -#define I2C_CNTRL2_START (0x00000100) -#define I2C_CNTRL2_WR_STATUS (0x00010000) -#define I2C_CNTRL2_RD_STATUS (0x00020000) -#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) -#define I2C_CNTRL2_I2C_CFGERR (0x08000000) -#define I2C_CNTRL2_I2C_CMPLT (0x10000000) - -/* I2C_CNTRL2 : Read/Write Bit Mask Definition */ -#define I2C_CNTRL2_RWMASK (0x0000011f) - -/* I2C_CNTRL2 : Unused/Reserved bits Definition */ -#define I2C_CNTRL2_RESERVED (0xe3fcfee0) - -/* I2C_RD_DATA : Reset Value */ -#define I2C_RD_DATA_RESET_VALUE (0x00000000) - -/* I2C_RD_DATA : Register Bits Masks Definitions */ -#define I2C_RD_DATA_RBYTE0 (0x000000ff) -#define I2C_RD_DATA_RBYTE1 (0x0000ff00) -#define I2C_RD_DATA_RBYTE2 (0x00ff0000) -#define I2C_RD_DATA_RBYTE3 (0xff000000) - -/* I2C_RD_DATA : Read/Write Bit Mask Definition */ -#define I2C_RD_DATA_RWMASK (0x00000000) - -/* I2C_RD_DATA : Unused/Reserved bits Definition */ -#define I2C_RD_DATA_RESERVED (0x00000000) - -/* I2C_TX_DATA : Reset Value */ -#define I2C_TX_DATA_RESET_VALUE (0x00000000) - -/* I2C_TX_DATA : Register Bits Masks Definitions */ -#define I2C_TX_DATA_TBYTE0 (0x000000ff) -#define I2C_TX_DATA_TBYTE1 (0x0000ff00) -#define I2C_TX_DATA_TBYTE2 (0x00ff0000) -#define I2C_TX_DATA_TBYTE3 (0xff000000) - -/* I2C_TX_DATA : Read/Write Bit Mask Definition */ -#define I2C_TX_DATA_RWMASK (0xffffffff) - -/* I2C_TX_DATA : Unused/Reserved bits Definition */ -#define I2C_TX_DATA_RESERVED (0x00000000) - -#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */ -#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */ - -#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ - -/* I2C status codes */ - -#define TSI108_I2C_SUCCESS 0 -#define TSI108_I2C_PARAM_ERR 1 -#define TSI108_I2C_TIMEOUT_ERR 2 -#define TSI108_I2C_IF_BUSY 3 -#define TSI108_I2C_IF_ERROR 4 - -#endif /* _TSI108_H_ */ |