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-rw-r--r--arch/sh/include/asm/cpu_sh4.h2
-rw-r--r--arch/sh/include/asm/cpu_sh7785.h119
-rw-r--r--doc/README.sh1
-rw-r--r--drivers/serial/serial_sh.c1
-rw-r--r--drivers/serial/serial_sh.h6
-rw-r--r--scripts/config_whitelist.txt1
6 files changed, 1 insertions, 129 deletions
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index 977b648..5fc9c96 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -42,8 +42,6 @@
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
-#elif defined (CONFIG_CPU_SH7785)
-# include <asm/cpu_sh7785.h>
#else
# error "Unknown SH4 variant"
#endif
diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h
deleted file mode 100644
index b038895..0000000
--- a/arch/sh/include/asm/cpu_sh7785.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _ASM_CPU_SH7785_H_
-#define _ASM_CPU_SH7785_H_
-
-/*
- * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
-
-/* Exceptions */
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-
-/* Cache Controller */
-#define CCR 0xFF00001C
-#define QACR0 0xFF000038
-#define QACR1 0xFF00003C
-#define RAMCR 0xFF000074
-
-/* Watchdog Timer and Reset */
-#define WTCNT WDTCNT
-#define WDTST 0xFFCC0000
-#define WDTCSR 0xFFCC0004
-#define WDTBST 0xFFCC0008
-#define WDTCNT 0xFFCC0010
-#define WDTBCNT 0xFFCC0018
-
-/* Timer Unit */
-#define TMU_BASE 0xFFD80000
-
-/* Serial Communication Interface with FIFO */
-#define SCIF1_BASE 0xffeb0000
-
-/* LBSC */
-#define MMSELR 0xfc400020
-#define LBSC_BASE 0xff800000
-#define BCR (LBSC_BASE + 0x1000)
-#define CS0BCR (LBSC_BASE + 0x2000)
-#define CS1BCR (LBSC_BASE + 0x2010)
-#define CS2BCR (LBSC_BASE + 0x2020)
-#define CS3BCR (LBSC_BASE + 0x2030)
-#define CS4BCR (LBSC_BASE + 0x2040)
-#define CS5BCR (LBSC_BASE + 0x2050)
-#define CS6BCR (LBSC_BASE + 0x2060)
-#define CS0WCR (LBSC_BASE + 0x2008)
-#define CS1WCR (LBSC_BASE + 0x2018)
-#define CS2WCR (LBSC_BASE + 0x2028)
-#define CS3WCR (LBSC_BASE + 0x2038)
-#define CS4WCR (LBSC_BASE + 0x2048)
-#define CS5WCR (LBSC_BASE + 0x2058)
-#define CS6WCR (LBSC_BASE + 0x2068)
-#define CS5PCR (LBSC_BASE + 0x2070)
-#define CS6PCR (LBSC_BASE + 0x2080)
-
-/* PCI Controller */
-#define SH7780_PCIECR 0xFE000008
-#define SH7780_PCIVID 0xFE040000
-#define SH7780_PCIDID 0xFE040002
-#define SH7780_PCICMD 0xFE040004
-#define SH7780_PCISTATUS 0xFE040006
-#define SH7780_PCIRID 0xFE040008
-#define SH7780_PCIPIF 0xFE040009
-#define SH7780_PCISUB 0xFE04000A
-#define SH7780_PCIBCC 0xFE04000B
-#define SH7780_PCICLS 0xFE04000C
-#define SH7780_PCILTM 0xFE04000D
-#define SH7780_PCIHDR 0xFE04000E
-#define SH7780_PCIBIST 0xFE04000F
-#define SH7780_PCIIBAR 0xFE040010
-#define SH7780_PCIMBAR0 0xFE040014
-#define SH7780_PCIMBAR1 0xFE040018
-#define SH7780_PCISVID 0xFE04002C
-#define SH7780_PCISID 0xFE04002E
-#define SH7780_PCICP 0xFE040034
-#define SH7780_PCIINTLINE 0xFE04003C
-#define SH7780_PCIINTPIN 0xFE04003D
-#define SH7780_PCIMINGNT 0xFE04003E
-#define SH7780_PCIMAXLAT 0xFE04003F
-#define SH7780_PCICID 0xFE040040
-#define SH7780_PCINIP 0xFE040041
-#define SH7780_PCIPMC 0xFE040042
-#define SH7780_PCIPMCSR 0xFE040044
-#define SH7780_PCIPMCSRBSE 0xFE040046
-#define SH7780_PCI_CDD 0xFE040047
-#define SH7780_PCICR 0xFE040100
-#define SH7780_PCILSR0 0xFE040104
-#define SH7780_PCILSR1 0xFE040108
-#define SH7780_PCILAR0 0xFE04010C
-#define SH7780_PCILAR1 0xFE040110
-#define SH7780_PCIIR 0xFE040114
-#define SH7780_PCIIMR 0xFE040118
-#define SH7780_PCIAIR 0xFE04011C
-#define SH7780_PCICIR 0xFE040120
-#define SH7780_PCIAINT 0xFE040130
-#define SH7780_PCIAINTM 0xFE040134
-#define SH7780_PCIBMIR 0xFE040138
-#define SH7780_PCIPAR 0xFE0401C0
-#define SH7780_PCIPINT 0xFE0401CC
-#define SH7780_PCIPINTM 0xFE0401D0
-#define SH7780_PCIMBR0 0xFE0401E0
-#define SH7780_PCIMBMR0 0xFE0401E4
-#define SH7780_PCIMBR1 0xFE0401E8
-#define SH7780_PCIMBMR1 0xFE0401EC
-#define SH7780_PCIMBR2 0xFE0401F0
-#define SH7780_PCIMBMR2 0xFE0401F4
-#define SH7780_PCIIOBR 0xFE0401F8
-#define SH7780_PCIIOBMR 0xFE0401FC
-#define SH7780_PCICSCR0 0xFE040210
-#define SH7780_PCICSCR1 0xFE040214
-#define SH7780_PCICSAR0 0xFE040218
-#define SH7780_PCICSAR1 0xFE04021C
-#define SH7780_PCIPDR 0xFE040220
-
-#endif /* _ASM_CPU_SH7780_H_ */
diff --git a/doc/README.sh b/doc/README.sh
index 6baee08..667c797 100644
--- a/doc/README.sh
+++ b/doc/README.sh
@@ -94,7 +94,6 @@ U-Boot for Renesas SuperH
I plan to support the following CPUs and boards.
5.1. CPUs
- SH7751R(SH4)
- - SH7785(SH4)
5.2. Boards
- Many boards ;-)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index c934d5f..e6fe5c7 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -21,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
static int scif_rxfill(struct uart_port *port)
{
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index c6f4778..887dd19 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -170,8 +170,7 @@ struct uart_port {
# define SCSCR_INIT(port) 0x3a
#endif
-#elif defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
+#elif defined(CONFIG_CPU_SH7786)
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
@@ -247,7 +246,6 @@ struct uart_port {
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \
defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786) || \
defined(CONFIG_CPU_SHX3)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
@@ -586,7 +584,6 @@ SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
@@ -726,7 +723,6 @@ static inline int sci_rxd_in(struct uart_port *port)
*/
#if (defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)) && \
!defined(CONFIG_SH_SH2007)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index ba8493f..995811c 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -285,7 +285,6 @@ CONFIG_CPU_SH7753
CONFIG_CPU_SH7757
CONFIG_CPU_SH7763
CONFIG_CPU_SH7780
-CONFIG_CPU_SH7785
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CQSPI_REF_CLK
generated by cgit v1.1 at 2024-11-12 17:53:24 +0000