diff options
| -rw-r--r-- | arch/arm/mach-mvebu/armada8k/cpu.c | 58 | ||||
| -rw-r--r-- | doc/mvebu/armada-8k-memory.txt | 56 |
2 files changed, 101 insertions, 13 deletions
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 2719d68..2325e9a 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -21,7 +21,33 @@ DECLARE_GLOBAL_DATA_PTR; #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84) #define RFU_SW_RESET_OFFSET 0 +/* + * The following table includes all memory regions for Armada 7k and + * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets + * define these regions at the beginning of the struct so that they + * can be easier removed later dynamically if an Armada 7k device is detected. + * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt + */ +#define ARMADA_7K8K_COMMON_REGIONS_START 2 static struct mm_region mvebu_mem_map[] = { + /* Armada 80x0 memory regions include the CP1 (slave) units */ + { + /* SRAM, MMIO regions - CP110 slave region */ + .phys = 0xf4000000UL, + .virt = 0xf4000000UL, + .size = 0x02000000UL, /* 32MiB internal registers */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { + /* PCI CP1 regions */ + .phys = 0xfa000000UL, + .virt = 0xfa000000UL, + .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + /* Armada 80x0 and 70x0 common memory regions start here */ { /* RAM */ .phys = 0x0UL, @@ -47,29 +73,35 @@ static struct mm_region mvebu_mem_map[] = { PTE_BLOCK_NON_SHARE }, { - /* SRAM, MMIO regions - CP110 slave region */ - .phys = 0xf4000000UL, - .virt = 0xf4000000UL, - .size = 0x02000000UL, /* 32MiB internal registers */ + /* PCI CP0 regions */ + .phys = 0xf6000000UL, + .virt = 0xf6000000UL, + .size = 0x04000000UL, /* 64MiB CP110 master PCI space */ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, { - /* PCI regions */ - .phys = 0xf8000000UL, - .virt = 0xf8000000UL, - .size = 0x08000000UL, /* 128MiB PCI space (master & slave) */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* List terminator */ 0, } }; struct mm_region *mem_map = mvebu_mem_map; +void enable_caches(void) +{ + /* + * Armada 7k is not equipped with the CP110 slave CP. In case this + * code runs on an Armada 7k device, lets remove the CP110 slave + * entries from the memory mapping by moving the start to the + * common regions. + */ + if (of_machine_is_compatible("marvell,armada7040")) + mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START]; + + icache_enable(); + dcache_enable(); +} + void reset_cpu(ulong ignored) { u32 reg; diff --git a/doc/mvebu/armada-8k-memory.txt b/doc/mvebu/armada-8k-memory.txt new file mode 100644 index 0000000..064518e --- /dev/null +++ b/doc/mvebu/armada-8k-memory.txt @@ -0,0 +1,56 @@ + Memory Layout on Armada-8k SoC's + ================================ + +The below desribes the physical memory layout for Marvell's Armada-8k SoC's. + +This assumes that the SoC includes Dual CP configuration, in case the flavor is using +a single CP configuration, then all secondary-CP mappings are invalid. + +All "Reserved" areas below, are kept for future usage. + +Start End Use +-------------------------------------------------------------------------- +0x00000000 0xEFFFFFFF DRAM + +0xF0000000 0xF0FFFFFF AP Internal registers space + +0xF1000000 0xF1FFFFFF Reserved. + +0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers + space. + +0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers + space. + +0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space. + +0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space. + +0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space. + +0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space. + +0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space. + +0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space. + +0xF9030000 0xF9FFFFFF Reserved. + +0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space. + +0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space. + +0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space. + +0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space. + +0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space. + +0xFD020000 0xFD02FFFF CP-1 / PCIe#2 IO space. + +0xFD030000 0xFFEFFFFF Reserved. + +0xFFF00000 0xFFFFFFFF Bootrom + +0x100000000 <DRAM Size>-1 DRAM + |