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author | Matthew McClintock <msm@freescale.com> | 2012-08-13 10:00:40 +0000 |
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committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 10:24:17 -0500 |
commit | 02ea538ce9fa8325f7d15c69cf87c950c5fe1f57 (patch) | |
tree | 15066f5b6df8b756f4fbb264ccf32522d8e27dbf /nand_spl/board/freescale/p1023rds/Makefile | |
parent | 8c454047fe9c08a51410dca01b945cdcecb18b7e (diff) | |
download | u-boot-02ea538ce9fa8325f7d15c69cf87c950c5fe1f57.zip u-boot-02ea538ce9fa8325f7d15c69cf87c950c5fe1f57.tar.gz u-boot-02ea538ce9fa8325f7d15c69cf87c950c5fe1f57.tar.bz2 |
nand_spl: p1023rds: wait before enabling DDR controller
We have a requirement to wait a period of time before enabling the
DDR controller
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl/board/freescale/p1023rds/Makefile')
-rw-r--r-- | nand_spl/board/freescale/p1023rds/Makefile | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 168e868..da43521 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### |