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| author | Marek Vasut <marex@denx.de> | 2020-12-01 11:34:48 +0100 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2021-01-13 09:52:58 +0100 |
| commit | 69ea30e688c4171830b94cd56d936ef6456877df (patch) | |
| tree | 6d4f01244e1c32435ae566aa36332936ce3d3898 /lib | |
| parent | 635e233b220b7fa4f4e8e8623f971b5cf66c4856 (diff) | |
| download | u-boot-69ea30e688c4171830b94cd56d936ef6456877df.zip u-boot-69ea30e688c4171830b94cd56d936ef6456877df.tar.gz u-boot-69ea30e688c4171830b94cd56d936ef6456877df.tar.bz2 | |
ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
To permit PLL4P to run at faster frequency, use MCO2 as a divider.
The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to
50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback
clock are fed back in via pin PA1.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
Diffstat (limited to 'lib')
0 files changed, 0 insertions, 0 deletions