aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorWolfgang Denk <wd@pollux.(none)>2005-12-04 00:40:34 +0100
committerWolfgang Denk <wd@pollux.(none)>2005-12-04 00:40:34 +0100
commitf013dacf0a90667fbefe35580f8031a84caeb65e (patch)
tree7e6f5ecf1ce7d800c13b0342ba10d67486c52636 /include
parentc75eba3b4140187cd0d9bd8049f5df4c49b6889b (diff)
downloadu-boot-f013dacf0a90667fbefe35580f8031a84caeb65e.zip
u-boot-f013dacf0a90667fbefe35580f8031a84caeb65e.tar.gz
u-boot-f013dacf0a90667fbefe35580f8031a84caeb65e.tar.bz2
Code cleanup, especially MIPS for GCC 4.x
Diffstat (limited to 'include')
-rw-r--r--include/configs/TQM834x.h6
-rw-r--r--include/configs/o2dnt.h2
2 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ba2f4ea..41f44c5 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -95,14 +95,14 @@
* When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
* banks has to be determined at runtime and stored in a gloabl variable
* tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
- * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
* should be made sufficiently large to accomodate the number of banks that
- * might acutally be detected. Since most (all?) Flash related functions use
+ * might actually be detected. Since most (all?) Flash related functions use
* CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
* defined as tqm834x_num_flash_banks.
*/
#define CFG_MAX_FLASH_BANKS_DETECT 2
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLY__
extern int tqm834x_num_flash_banks;
#endif
#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 981651a..d7d27e5 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -277,7 +277,7 @@
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
-/*
+/*
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
*/
#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */