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| author | Tom Rini <trini@konsulko.com> | 2022-11-19 18:45:39 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-05 16:08:38 -0500 |
| commit | be3bea2ba33bc731dbca72576f8b30c587c2e3b3 (patch) | |
| tree | 66dd696e40b7c46e0fc899d8462604e42ed7d73f /include | |
| parent | a9c3bce3626686efc9528c048e9296bb734d988c (diff) | |
| download | u-boot-be3bea2ba33bc731dbca72576f8b30c587c2e3b3.zip u-boot-be3bea2ba33bc731dbca72576f8b30c587c2e3b3.tar.gz u-boot-be3bea2ba33bc731dbca72576f8b30c587c2e3b3.tar.bz2 | |
Convert CONFIG_VSC7385_ENET et al to Kconfig
This converts the following to Kconfig:
CONFIG_VSC7385_ENET
CONFIG_VSC9953
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC837XERDB.h | 5 | ||||
| -rw-r--r-- | include/configs/T104xRDB.h | 1 | ||||
| -rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 3 |
3 files changed, 0 insertions, 9 deletions
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index de63a0f..95a9019 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -14,11 +14,6 @@ * High Level Configuration Options */ -/* - * On-board devices - */ -#define CONFIG_VSC7385_ENET - /* System performance - define the value i.e. CONFIG_SYS_XXX */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index d3fd105..b693805 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -385,7 +385,6 @@ /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB #define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c8acce8..9738e9f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -13,7 +13,6 @@ #include <linux/stringify.h> #if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x5c @@ -43,7 +42,6 @@ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x64 @@ -63,7 +61,6 @@ #endif #if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 |