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author | Marian Balakowicz <m8@semihalf.com> | 2006-04-08 19:08:06 +0200 |
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committer | Marian Balakowicz <m8@semihalf.com> | 2006-04-08 19:08:06 +0200 |
commit | 6db39708117d6391a72f3fc3ea7860231b630270 (patch) | |
tree | 1c69fc84c3f615fe60217096c2947744c72e3528 /include | |
parent | 2fc000d756920b340945a74ec1214a34d9e84858 (diff) | |
download | u-boot-6db39708117d6391a72f3fc3ea7860231b630270.zip u-boot-6db39708117d6391a72f3fc3ea7860231b630270.tar.gz u-boot-6db39708117d6391a72f3fc3ea7860231b630270.tar.bz2 |
Fix JFFS2 support for legacy NAND driver.
Some more NAND cleanup and small fixes.
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/CATcenter.h | 19 | ||||
-rw-r--r-- | include/configs/CPU86.h | 2 | ||||
-rw-r--r-- | include/configs/IDS8247.h | 1 | ||||
-rw-r--r-- | include/configs/NC650.h | 2 | ||||
-rw-r--r-- | include/configs/NETTA.h | 1 | ||||
-rw-r--r-- | include/configs/RBC823.h | 2 | ||||
-rw-r--r-- | include/configs/VCMA9.h | 1 | ||||
-rw-r--r-- | include/configs/delta.h | 3 | ||||
-rw-r--r-- | include/configs/omap2420h4.h | 1 | ||||
-rw-r--r-- | include/configs/stxxtc.h | 1 |
10 files changed, 19 insertions, 14 deletions
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index ffe89cb..7ec4599 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -193,6 +193,8 @@ */ #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define NAND_BIG_DELAY_US 25 /* For CATcenter there is only NAND on the module */ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -218,9 +220,9 @@ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -231,9 +233,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -244,8 +246,7 @@ } \ } while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -258,7 +259,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -271,7 +272,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -284,7 +285,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 1e9a99e..16a9ea5 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -178,8 +178,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CFG_NAND_LEGACY - /* * Miscellaneous configurable options */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index aaa44c5..29eb874 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -236,6 +236,7 @@ */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) +#define CFG_NAND_LEGACY #define CFG_NAND0_BASE 0xE1000000 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 371ea17..3c59df4 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -217,6 +217,8 @@ /* * NAND flash support */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 #define NAND_ChipID_UNKNOWN 0x00 #define SECTORSIZE 512 diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 1bcd88d..25b6345 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -609,6 +609,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_UNSAFE diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 21945a3..242c837 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -326,8 +326,6 @@ /************************************************************ * Disk-On-Chip configuration ************************************************************/ -#define CFG_NAND_LEGACY - #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ #define CFG_DOC_SHORT_TIMEOUT #define CFG_DOC_SUPPORT_2000 diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 3f29190..5f48a70 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -248,6 +248,7 @@ */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) +#define CFG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/delta.h b/include/configs/delta.h index b42a7e2..31feaa3 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -162,7 +162,8 @@ * NAND Flash */ /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ -#define CONFIG_NEW_NAND_CODE +#undef CFG_NAND_LEGACY + #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ #undef CFG_NAND1_BASE diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 12252ac..5837461 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -132,6 +132,7 @@ /* * Board NAND Info. */ +#define CFG_NAND_LEGACY #define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index be6c36c..614a046 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -436,6 +436,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE |