diff options
author | Tom Rini <trini@konsulko.com> | 2020-05-05 09:08:53 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-05-05 09:08:53 -0400 |
commit | 191ee8aac60d6b828ee5f933ab2c6aceda167082 (patch) | |
tree | 4c0c12e8e510475050a7ca42ee6da6e076805bad /include | |
parent | 425fefa9a36ca729b5088ca5381f63f8d95a2f8e (diff) | |
parent | 9e36eae1249f477275a607736eda75e663d1b57c (diff) | |
download | u-boot-191ee8aac60d6b828ee5f933ab2c6aceda167082.zip u-boot-191ee8aac60d6b828ee5f933ab2c6aceda167082.tar.gz u-boot-191ee8aac60d6b828ee5f933ab2c6aceda167082.tar.bz2 |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- Add DM model for P1010RDB
- Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB,
MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB,
P5040DS
- Fix reference to READM.qe_firmware
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/MPC8548CDS.h | 9 | ||||
-rw-r--r-- | include/configs/P1010RDB.h | 50 | ||||
-rw-r--r-- | include/configs/P1022DS.h | 4 | ||||
-rw-r--r-- | include/configs/P2041RDB.h | 9 | ||||
-rw-r--r-- | include/configs/T102xQDS.h | 10 | ||||
-rw-r--r-- | include/configs/T102xRDB.h | 8 | ||||
-rw-r--r-- | include/configs/T1040QDS.h | 7 | ||||
-rw-r--r-- | include/configs/T104xRDB.h | 10 | ||||
-rw-r--r-- | include/configs/T208xQDS.h | 7 | ||||
-rw-r--r-- | include/configs/T208xRDB.h | 10 | ||||
-rw-r--r-- | include/configs/T4240QDS.h | 13 | ||||
-rw-r--r-- | include/configs/T4240RDB.h | 9 | ||||
-rw-r--r-- | include/configs/corenet_ds.h | 8 | ||||
-rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 9 | ||||
-rw-r--r-- | include/fsl_qe.h | 3 |
15 files changed, 137 insertions, 29 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a68d190..b779623 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. + * Copyright 2020 NXP */ /* @@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#else +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* EEPROM */ #define CONFIG_ID_EEPROM diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 60e8904..ce48ae1 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -113,8 +114,6 @@ #if defined(CONFIG_PCI) #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* @@ -122,19 +121,13 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else @@ -142,27 +135,45 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ +#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + #if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" #elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -522,17 +533,22 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define I2C_PCA9557_ADDR1 0x18 #define I2C_PCA9557_ADDR2 0x19 #define I2C_PCA9557_BUS_NUM 0 +#define CONFIG_SYS_I2C_FSL /* I2C EEPROM */ #if defined(CONFIG_TARGET_P1010RDB_PB) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5cc2e06..f8b035f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -359,8 +359,8 @@ #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 @@ -368,6 +368,8 @@ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} +#endif +#define CONFIG_SYS_I2C_FSL /* * I2C2 EEPROM diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0dcba7d..dfc8458 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -267,14 +268,20 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL + /* * RapidIO diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 20c0534..7f9e0c8 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -437,14 +438,20 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ @@ -460,6 +467,7 @@ unsigned long get_board_ddr_clk(void); /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 /* * RTC configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 094795c..2b43b81 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -434,15 +435,20 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index cda8251..ad8efb3 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -1,5 +1,6 @@ /* * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * * See file CREDITS for list of people who contributed to this * project. @@ -360,6 +361,8 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ + +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ @@ -374,6 +377,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#endif + +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ @@ -385,6 +391,7 @@ unsigned long get_board_ddr_clk(void); /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 /* * RTC configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index bc65118..7d15910 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __CONFIG_H @@ -27,6 +28,7 @@ #define CONFIG_SPL_SKIP_RELOCATE #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_DM_I2C #endif #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 @@ -459,8 +461,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 @@ -473,7 +475,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 @@ -484,6 +491,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 /* * RTC configuration diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 96801e5..aed2e87 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -385,8 +386,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -399,6 +400,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index a90ea11..e0ef2b2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -333,8 +334,8 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F @@ -347,6 +348,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_I2C2_SPEED 100000 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL + #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 91a7c70..5f91a52 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -280,6 +280,19 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#else +#undef CONFIG_SYS_I2C +#undef CONFIG_SYS_FSL_I2C2_OFFSET +#undef CONFIG_SYS_FSL_I2C2_SLAVE +#undef CONFIG_SYS_FSL_I2C2_SPEED +#undef CONFIG_SYS_FSL_I2C_SLAVE +#undef CONFIG_SYS_FSL_I2C_SPEED +#undef CONFIG_SYS_FSL_I2C_OFFSET +#endif + +#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 31cb1cf..ce7634f 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -159,12 +160,18 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL /* * General PCI diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index b2c86ff..26f534a 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -276,14 +277,19 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* * RapidIO diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c42f1a9..d59fd03 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ /* @@ -537,8 +538,8 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 @@ -546,6 +547,12 @@ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif + +#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ diff --git a/include/fsl_qe.h b/include/fsl_qe.h index d4eba82..6e44cbd 100644 --- a/include/fsl_qe.h +++ b/include/fsl_qe.h @@ -227,7 +227,8 @@ typedef enum qe_clock { /* Structure that defines QE firmware binary files. * - * See doc/README.qe_firmware for a description of these fields. + * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for + * a description of these fields. */ struct qe_firmware { struct qe_header { |