Revert most of the series for adding vexpress_aemv8r supportWIP/03Sep2021-next

Per a request from Andre Przywara and agreed with by Peter Hoyes, the
vexpress aemv8r support wasn't quite ready to be merged, but the
discussion had moved off list.  We should keep the first patch in the
series for now, but revert the rest.  This reverts the following
commits:

e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs
30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1
b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant
2f5b7b74903f armv8: Add ARMv8 MPU configuration logic
37a757e227cc armv8: Ensure EL1&0 VMSA is enabled

Signed-off-by: Tom Rini <trini@konsulko.com>

1 files changed, 21 insertions, 37 deletions

diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8a.h
index 3447f02..df22584 100644
--- a/include/configs/vexpress_aemv8.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -10,36 +10,30 @@
 #define CONFIG_REMAKE_ELF
 
 /* Link Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#else
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 /* ATF loads u-boot here for BASE_FVP model */
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#elif CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
 #endif
 
 #define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */
 
 /* CS register bases for the original memory map. */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
-#define V2M_BASE			0x00000000
-#define V2M_PA_BASE			0x80000000
-#else
-#define V2M_BASE			0x80000000
-#define V2M_PA_BASE			0x00000000
-#endif
-
-#define V2M_PA_CS0			(V2M_PA_BASE + 0x00000000)
-#define V2M_PA_CS1			(V2M_PA_BASE + 0x14000000)
-#define V2M_PA_CS2			(V2M_PA_BASE + 0x18000000)
-#define V2M_PA_CS3			(V2M_PA_BASE + 0x1c000000)
-#define V2M_PA_CS4			(V2M_PA_BASE + 0x0c000000)
-#define V2M_PA_CS5			(V2M_PA_BASE + 0x10000000)
+#define V2M_PA_CS0			0x00000000
+#define V2M_PA_CS1			0x14000000
+#define V2M_PA_CS2			0x18000000
+#define V2M_PA_CS3			0x1c000000
+#define V2M_PA_CS4			0x0c000000
+#define V2M_PA_CS5			0x10000000
 
 #define V2M_PERIPH_OFFSET(x)		(x << 16)
 #define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
 #define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
 #define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
 
+#define V2M_BASE			0x80000000
+
 /* Common peripherals relative to CS7. */
 #define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
 #define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
@@ -74,27 +68,27 @@
 #define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
 
 /* Generic Timer Definitions */
-#define COUNTER_FREQUENCY		100000000	/* 100MHz */
+#define COUNTER_FREQUENCY		24000000	/* 24MHz */
 
 /* Generic Interrupt Controller Definitions */
 #ifdef CONFIG_GICV3
-#define GICD_BASE			(V2M_PA_BASE + 0x2f000000)
-#define GICR_BASE			(V2M_PA_BASE + 0x2f100000)
+#define GICD_BASE			(0x2f000000)
+#define GICR_BASE			(0x2f100000)
 #else
 
-#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#define GICD_BASE			(0x2f000000)
+#define GICC_BASE			(0x2c000000)
+#elif CONFIG_TARGET_VEXPRESS64_JUNO
 #define GICD_BASE			(0x2C010000)
 #define GICC_BASE			(0x2C02f000)
-#else
-#define GICD_BASE			(V2M_PA_BASE + 0x2f000000)
-#define GICC_BASE			(V2M_PA_BASE + 0x2c000000)
 #endif
 #endif /* !CONFIG_GICV3 */
 
 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
 /* The Vexpress64 simulators use SMSC91C111 */
 #define CONFIG_SMC91111			1
-#define CONFIG_SMC91111_BASE		(V2M_PA_BASE + 0x01A000000)
+#define CONFIG_SMC91111_BASE		(0x01A000000)
 #endif
 
 /* PL011 Serial Configuration */
@@ -119,7 +113,7 @@
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 #define PHYS_SDRAM_2			(0x880000000)
 #define PHYS_SDRAM_2_SIZE		0x180000000
-#elif CONFIG_NR_DRAM_BANKS == 2
+#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
 #define PHYS_SDRAM_2			(0x880000000)
 #define PHYS_SDRAM_2_SIZE		0x80000000
 #endif
@@ -206,12 +200,6 @@
 				"  booti $kernel_addr - $fdt_addr; " \
 				"fi"
 #endif
-
-#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP
-#define CONFIG_EXTRA_ENV_SETTINGS	\
-				"kernel_addr=0x00800000\0"	\
-				"fdt_addr=0x03000000\0"		\
-				"boot_addr=0x0007f800\0"
 #endif
 
 /* Monitor Command Prompt */
@@ -225,7 +213,7 @@
 /* Store environment at top of flash in the same location as blank.img */
 /* in the Juno firmware. */
 #else
-#define CONFIG_SYS_FLASH_BASE		(V2M_PA_BASE + 0x0C000000)
+#define CONFIG_SYS_FLASH_BASE		0x0C000000
 /* 256 x 256KiB sectors */
 #define CONFIG_SYS_MAX_FLASH_SECT	256
 /* Store environment at top of flash */
@@ -242,8 +230,4 @@
 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
 #define FLASH_MAX_SECTOR_SIZE		0x00040000
 
-#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
-#define CONFIG_ARMV8_SWITCH_TO_EL1
-#endif
-
 #endif /* __VEXPRESS_AEMV8A_H */