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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-07-19 15:54:33 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-08-02 09:46:02 -0700 |
| commit | 37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299 (patch) | |
| tree | 54f6761e38d1f1ef2769dc2dd0c0faaa04765477 /include/fsl_mmdc.h | |
| parent | 9c3fca2a79be3d9d67d7766bbd85efc941bcb237 (diff) | |
| download | u-boot-37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299.zip u-boot-37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299.tar.gz u-boot-37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299.tar.bz2 | |
armv8: ls1012a: Update Refresh cycle for DDR
Refresh cycle value must be selected based on the frequency
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
value should be 0x0f3c8000.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_mmdc.h')
| -rw-r--r-- | include/fsl_mmdc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index 833696b..a939d89 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -43,7 +43,7 @@ #define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067 -#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000 +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000 #define START_REFRESH 0x00000001 |