Merge git://git.denx.de/u-boot-fsl-qoriq

- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs

8 files changed, 547 insertions, 7 deletions

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 324dba2..9bbf348 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -6,7 +6,6 @@
 #ifndef __LS1012A_COMMON_H
 #define __LS1012A_COMMON_H
 
-#define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 49b0141..662b573 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -26,7 +26,6 @@
 #endif
 
 #define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_GICV2
 
 #include <asm/arch/stream_id_lsch2.h>
@@ -209,7 +208,7 @@
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
-#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4a08)
+#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4A00)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
@@ -255,6 +254,8 @@
 	"fdtheader_addr_r=0x80100000\0"		\
 	"kernelheader_addr_r=0x80200000\0"	\
 	"kernel_addr_r=0x81000000\0"		\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
 	"fdt_addr_r=0x90000000\0"		\
 	"load_addr=0xa0000000\0"		\
 	"kernelheader_addr=0x60800000\0"	\
@@ -306,6 +307,12 @@
 		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 		"bootm $load_addr#$board\0"	    \
+	"nand_bootcmd=echo Trying load from NAND..;"	\
+		"nand info; nand read $load_addr "	\
+		"$kernel_start $kernel_size; env exists secureboot "	\
+		"&& nand read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	\
 	"sd_bootcmd=echo Trying load from SD ..;"       \
 		"mmcinfo; mmc read $load_addr "         \
 		"$kernel_addr_sd $kernel_size_sd && "     \
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 6e36c93..0266681 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -26,7 +26,6 @@
 #endif
 
 #define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 95e6786..b663937 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -21,7 +21,6 @@
 #endif
 
 #define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
 
 #include <asm/arch/stream_id_lsch3.h>
 #include <asm/arch/config.h>
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 235a757..0a6c90d 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -8,9 +8,7 @@
 #define __LS2_COMMON_H
 
 #define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
 
 #include <asm/arch/stream_id_lsch3.h>
 #include <asm/arch/config.h>
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
new file mode 100644
index 0000000..4b5608b
--- /dev/null
+++ b/include/configs/lx2160a_common.h
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_COMMON_H
+#define __LX2_COMMON_H
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_MEMAC
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+/* DDR */
+#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE		0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
+#define CONFIG_SYS_SDRAM_SIZE			0x200000000UL
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x51
+#define SPD_EEPROM_ADDRESS2		0x52
+#define SPD_EEPROM_ADDRESS3		0x53
+#define SPD_EEPROM_ADDRESS4		0x54
+#define SPD_EEPROM_ADDRESS5		0x55
+#define SPD_EEPROM_ADDRESS6		0x56
+#define SPD_EEPROM_ADDRESS		SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
+#define CONFIG_SYS_MONITOR_LEN		(936 * 1024)
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* SMP Definitinos  */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+/* Generic Timer Definitions */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* Serial Port */
+#define CONFIG_PL01X_SERIAL
+#define CONFIG_PL011_CLOCK		(get_bus_freq(0) / 4)
+#define CONFIG_SYS_SERIAL0		0x21c0000
+#define CONFIG_SYS_SERIAL1		0x21d0000
+#define CONFIG_SYS_SERIAL2		0x21e0000
+#define CONFIG_SYS_SERIAL3		0x21f0000
+/*below might needs to be removed*/
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					(void *)CONFIG_SYS_SERIAL1, \
+					(void *)CONFIG_SYS_SERIAL2, \
+					(void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH		0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET	0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH		0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET	0x00F20000
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS	5000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT		0x8
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/* Qixis */
+#define CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR		0x66
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+
+#ifdef CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1		AHCI_BASE_ADDR1
+#define CONFIG_SYS_SATA2		AHCI_BASE_ADDR2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* USB */
+#ifdef CONFIG_USB
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
+/* FlexSPI */
+#ifdef CONFIG_NXP_FSPI
+#define NXP_FSPI_FLASH_SIZE		SZ_64M
+#define NXP_FSPI_FLASH_NUM		1
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+/* Initial environment variables */
+#define XSPI_MC_INIT_CMD			\
+	"env exists secureboot && "		\
+	"esbc_validate 0x20700000 && "		\
+	"esbc_validate 0x20740000 ;"		\
+	"fsl_mc start mc 0x20a00000 0x20e00000\0"
+
+#define SD_MC_INIT_CMD				\
+	"mmc read 0x80000000 0x5000 0x800;"	\
+	"mmc read 0x80100000 0x7000 0x800;"	\
+	"env exists secureboot && "		\
+	"mmc read 0x80700000 0x3800 0x10 && "	\
+	"mmc read 0x80740000 0x3A00 0x10 && "	\
+	"esbc_validate 0x80700000 && "		\
+	"esbc_validate 0x80740000 ;"		\
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+
+#define EXTRA_ENV_SETTINGS			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x7C0000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernelhdr_addr_sd=0x3E00\0"            \
+	"kernel_size_sd=0x1d000\0"              \
+	"kernelhdr_size_sd=0x10\0"              \
+	"console=ttyAMA0,38400n8\0"		\
+	BOOTENV					\
+	"mcmemsize=0x70000000\0"		\
+	XSPI_MC_INIT_CMD				\
+	"boot_scripts=lx2160ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_lx2160ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"scan_dev_for_boot="					\
+		"echo Scanning ${devtype} "			\
+			"${devnum}:${distro_bootpart}...; "	\
+		"for prefix in ${boot_prefixes}; do "		\
+			"run scan_dev_for_scripts; "		\
+		"done;\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} "	\
+			"${scriptaddr} ${prefix}${script}; "	\
+		"env exists secureboot && load ${devtype} "	\
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"
+
+#define XSPI_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x20780000; "			\
+			"env exists mcinitcmd && "			\
+			"fsl_mc lazyapply dpl 0x20d00000; "		\
+			"run distro_bootcmd;run xspi_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+#define SD_BOOTCOMMAND						\
+		"env exists mcinitcmd && mmcinfo; "		\
+		"mmc read 0x80001000 0x6800 0x800; "		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && mmc read 0x80780000 0x3C00 0x10 "		\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run sd_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 0) \
+	func(SCSI, scsi, 0)
+#include <config_distro_bootcmd.h>
+
+#endif /* __LX2_COMMON_H */
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
new file mode 100644
index 0000000..662e601
--- /dev/null
+++ b/include/configs/lx2160aqds.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __LX2_QDS_H
+#define __LX2_QDS_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK			0x07
+#define QIXIS_XMAP_SHIFT		5
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD		0x08
+#define NON_EXTENDED_DUTCFG
+#define QIXIS_SDID_MASK			0x07
+#define QIXIS_ESDHC_NO_ADAPTER		0x7
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_100		0x0
+#define QIXIS_SYSCLK_125		0x1
+#define QIXIS_SYSCLK_133		0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100		0x0
+#define QIXIS_DDRCLK_125		0x1
+#define QIXIS_DDRCLK_133		0x2
+
+#define BRDCFG4_EMI1SEL_MASK		0xF8
+#define BRDCFG4_EMI1SEL_SHIFT		3
+#define BRDCFG4_EMI2SEL_MASK		0x07
+#define BRDCFG4_EMI2SEL_SHIFT		0
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR		0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+#define CONFIG_VID_FLS_ENV		"lx2160aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			925
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+#define PWM_CHANNEL0                    0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM		0
+#define I2C_MUX_CH_RTC			0xB
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#ifndef __ASSEMBLY__
+u8 qixis_esdhc_detect_quirk(void);
+#endif
+#define CONFIG_ESDHC_DETECT_QUIRK  qixis_esdhc_detect_quirk()
+#endif
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME		"DPMAC17@rgmii-id"
+
+#define AQ_PHY_ADDR1		0x00
+#define AQ_PHY_ADDR2		0x01
+#define AQ_PHY_ADDR3		0x02
+#define AQ_PHY_ADDR4		0x03
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1	0x0
+
+#define INPHI_PHY_ADDR1		0x0
+#define INPHI_PHY_ADDR2		0x1
+
+#define RGMII_PHY_ADDR1		0x01
+#define RGMII_PHY_ADDR2		0x02
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	EXTRA_ENV_SETTINGS			\
+	"lx2160aqds_vdd_mv=800\0"		\
+	"BOARD=lx2160aqds\0"			\
+	"xspi_bootcmd=echo Trying load from flexspi..;"		\
+		"sf probe 0:0 && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$BOARD\0"			\
+	"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_QDS_H */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
new file mode 100644
index 0000000..972bb5e
--- /dev/null
+++ b/include/configs/lx2160ardb.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_RDB_H
+#define __LX2_RDB_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK			0x07
+#define QIXIS_XMAP_SHIFT		5
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD           0x08
+#define NON_EXTENDED_DUTCFG
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR		0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+#define CONFIG_VID_FLS_ENV		"lx2160ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			855
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+#define PWM_CHANNEL0                    0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM		4
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
+
+#define AQR107_PHY_ADDR1	0x04
+#define AQR107_PHY_ADDR2	0x05
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1	0x0
+#define INPHI_PHY_ADDR1		0x0
+
+#define RGMII_PHY_ADDR1		0x01
+#define RGMII_PHY_ADDR2		0x02
+
+#endif
+
+/* EMC2305 */
+#define I2C_MUX_CH_EMC2305		0x09
+#define I2C_EMC2305_ADDR		0x4D
+#define I2C_EMC2305_CMD		0x40
+#define I2C_EMC2305_PWM		0x80
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	           0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	           0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	    1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	EXTRA_ENV_SETTINGS			\
+	"lx2160ardb_vdd_mv=800\0"		\
+	"BOARD=lx2160ardb\0"			\
+	"xspi_bootcmd=echo Trying load from flexspi..;"		\
+		"sf probe 0:0 && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$BOARD\0"			\
+	"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_RDB_H */