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| author | David Lechner <david@lechnology.com> | 2018-03-14 20:36:30 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-03-22 16:32:24 -0400 |
| commit | dc73483a122960d094486fc58df953209bdb1edd (patch) | |
| tree | 34e76dffa523987d6a07a69421d5dc52ba5fd17c /include/configs/omapl138_lcdk.h | |
| parent | 7f9b50a27c10579cc87af8d3ef6a033cc8fe001a (diff) | |
| download | u-boot-dc73483a122960d094486fc58df953209bdb1edd.zip u-boot-dc73483a122960d094486fc58df953209bdb1edd.tar.gz u-boot-dc73483a122960d094486fc58df953209bdb1edd.tar.bz2 | |
davinci: omapl138_lcdk: fix PLL0 frequency
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT must be 600MHz max). It also uses a PLLM value outside of
the range given in the TRM (it says PLLM must in the range 0 to 0x1f).
So here is what we have currently:
PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec)
^ ^ ^
CLKIN PREDIV PLLM (out of spec)
input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result)
^ ^
PLLOUT POSTDIV
This changes the PLLM value to 18 and the POSTDIV value to 0 so that
PLLOUT is now within specification but we still get the desired
result.
PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec)
^ ^ ^
CLKIN PREDIV PLLM
input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result)
^ ^
PLLOUT POSTDIV
Fixes: 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
Signed-off-by: David Lechner <david@lechnology.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'include/configs/omapl138_lcdk.h')
| -rw-r--r-- | include/configs/omapl138_lcdk.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 12b266e..2a390bf 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -57,7 +57,8 @@ * PLL configuration */ -#define CONFIG_SYS_DA850_PLL0_PLLM 37 +/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ +#define CONFIG_SYS_DA850_PLL0_PLLM 18 #define CONFIG_SYS_DA850_PLL1_PLLM 21 /* |