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| author | Dirk Eibach <eibach@gdsys.de> | 2011-01-21 09:31:21 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-02-07 11:13:16 +0100 |
| commit | 2da0fc0d0fcdd991220cc120e5bc6d44991a5987 (patch) | |
| tree | c14838b5dbac4b29f646c72d0b460dd4c11dd83e /include/configs/iocon.h | |
| parent | 42d44f631c4e8e5359775bdc098f2fffde4e5c05 (diff) | |
| download | u-boot-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.zip u-boot-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.tar.gz u-boot-2da0fc0d0fcdd991220cc120e5bc6d44991a5987.tar.bz2 | |
ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/iocon.h')
| -rw-r--r-- | include/configs/iocon.h | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 5e61b11..9fcc643 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -131,6 +131,12 @@ int fpga_gpio_get(int pin); #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ /* + * OSD hardware + */ +#define CONFIG_SYS_MPC92469AC +#define CONFIG_SYS_CH7301 + +/* * FLASH organization */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ @@ -231,13 +237,15 @@ int fpga_gpio_get(int pin); #define CONFIG_SYS_EBC_PB1AP 0x92015480 #define CONFIG_SYS_EBC_PB1CR 0xFB858000 -/* Memory Bank 2 (FPGA) initialization */ -#define CONFIG_SYS_FPGA_BASE 0x7f100000 +/* Memory Bank 2 (FPGA0) initialization */ +#define CONFIG_SYS_FPGA0_BASE 0x7f100000 #define CONFIG_SYS_EBC_PB2AP 0x02825080 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000) +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000) + +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 -#define CONFIG_SYS_FPGA_RFL_LOW 0x0000 -#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe +#define CONFIG_SYS_FPGA_COUNT 1 /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 @@ -249,4 +257,11 @@ int fpga_gpio_get(int pin); #define CONFIG_SYS_LATCH1_RESET 0xffff #define CONFIG_SYS_LATCH1_BOOT 0xffff +/* + * OSD Setup + */ +#define CONFIG_SYS_MPC92469AC +#define CONFIG_SYS_CH7301 +#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT + #endif /* __CONFIG_H */ |