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| author | Peter Chubb <Peter.Chubb@data61.csiro.au> | 2016-08-30 22:54:46 +0000 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-09-01 09:24:30 -0700 |
| commit | b615267633996a9410a88b54a55965d8b021f6f8 (patch) | |
| tree | 2a3e8377ac5ef72bbc1fae56da520513c0971891 /include/configs/cei-tk1-som.h | |
| parent | 7932d3e4a7d23c8b9b9ecd50f1869eaf3e46ed49 (diff) | |
| download | u-boot-b615267633996a9410a88b54a55965d8b021f6f8.zip u-boot-b615267633996a9410a88b54a55965d8b021f6f8.tar.gz u-boot-b615267633996a9410a88b54a55965d8b021f6f8.tar.bz2 | |
ARM: tegra: Add support for TK1-SOM board from Colorado Engineering
The Colorado TK1 SOM is a small form factor board similar to the
Jetson TK1. The main differences lie in the pinmux, and in that the
PCIe controller is set to use in 4lanes+1lane, rather than 2+2.
The pinmux header here was generated from a spreadsheet provided by
Colorado Engineering using the tegra-pinmux scripts. The spreadsheet
was converted from v09 to v11 by me.
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/configs/cei-tk1-som.h')
| -rw-r--r-- | include/configs/cei-tk1-som.h | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h new file mode 100644 index 0000000..74fc377 --- /dev/null +++ b/include/configs/cei-tk1-som.h @@ -0,0 +1,73 @@ +/* + * (c) Copyright 2016, Data61 + * Commonwealth Scientific and Industrial Research Organisation (CSIRO) + * + * Based on jetson-tk1.h which is: + * (C) Copyright 2013-2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_AS3722_POWER + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* PCI host support */ +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_PCI + +/* General networking support */ + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define CONFIG_ARMV7_PSCI 1 +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + +#endif /* __CONFIG_H */ |