global: Move remaining CONFIG_SYS_* to CFG_SYS_*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

1 files changed, 114 insertions, 114 deletions

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 37dfe32..bee4b70 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -36,18 +36,18 @@
 
 #ifdef CONFIG_SPIFLASH
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
 #endif
 
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CFG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
 #endif
 
 #endif
@@ -63,7 +63,7 @@
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CFG_SYS_INIT_L2CSR0		L2CSR0_L2E
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
@@ -71,24 +71,24 @@
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CFG_SYS_INIT_L3_ADDR		0xFFFC0000
 /*
- * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
- * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
- * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
+ * (CFG_SYS_INIT_L3_VADDR) will be different.
  */
-#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
+#define CFG_SYS_INIT_L3_VADDR	0xFFFC0000
 #define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#define CFG_SYS_DCSRBAR		0xf0000000
+#define CFG_SYS_DCSRBAR_PHYS		0xf00000000ull
 
 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CFG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 #define SPD_EEPROM_ADDRESS	0x51
 
@@ -97,11 +97,11 @@
 /*
  * IFC Definitions
  */
-#define CONFIG_SYS_FLASH_BASE	0xe8000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE	0xe8000000
+#define CFG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CFG_SYS_FLASH_BASE)
 
 #define CFG_SYS_NOR_CSPR_EXT	(0xf)
-#define CFG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+#define CFG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
 				CSPR_PORT_SIZE_16 | \
 				CSPR_MSEL_NOR | \
 				CSPR_V)
@@ -128,7 +128,7 @@
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST	{CFG_SYS_FLASH_BASE_PHYS}
 
 /* CPLD on IFC */
 #define CPLD_LBMAP_MASK			0x3F
@@ -157,25 +157,25 @@
 #define CPLD_INT_MASK_TDMR2		0x01
 #endif
 
-#define CONFIG_SYS_CPLD_BASE	0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR2_EXT	(0xf)
-#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CPLD_BASE	0xffdf0000
+#define CFG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CFG_SYS_CPLD_BASE)
+#define CFG_SYS_CSPR2_EXT	(0xf)
+#define CFG_SYS_CSPR2	(CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR2	0x0
+#define CFG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR2	0x0
 /* CPLD Timing parameters for IFC CS2 */
-#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
 					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
 					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS2_FTIM3		0x0
+#define CFG_SYS_CS2_FTIM3		0x0
 
 /* NAND Flash on IFC */
 #define CFG_SYS_NAND_BASE		0xff800000
@@ -213,55 +213,55 @@
 #define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1		CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NOR_FTIM3
 #else
-#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0		CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1		CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1		CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 
 #define CONFIG_HWCONFIG
 
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+#define CFG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+#define CFG_SYS_INIT_RAM_ADDR_PHYS \
+	((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CFG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -269,13 +269,13 @@
  */
 #define CFG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
+#define CFG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
-#define CFG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CFG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CFG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CFG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3	(CFG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4	(CFG_SYS_CCSRBAR+0x11D600)
 
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
@@ -289,7 +289,7 @@
  */
 #define RTC
 #define CONFIG_RTC_DS1337               1
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CFG_SYS_I2C_RTC_ADDR         0x68
 
 /*DVI encoder*/
 #define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
@@ -344,58 +344,58 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_BMAN_NUM_PORTALS	10
+#define CFG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CFG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CFG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
+#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
+					CFG_SYS_BMAN_CENA_SIZE)
+#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
+#define CFG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CFG_SYS_QMAN_NUM_PORTALS	10
+#define CFG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CFG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CFG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
+					CFG_SYS_QMAN_CENA_SIZE)
+#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
+#define CFG_SYS_QMAN_SWP_ISDR_REG	0xE08
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_FMAN_ENET
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
+#define CFG_SYS_SGMII1_PHY_ADDR             0x03
 #elif defined(CONFIG_TARGET_T1040D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
+#define CFG_SYS_SGMII1_PHY_ADDR             0x01
 #elif defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
-#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
-#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
+#define CFG_SYS_SGMII1_PHY_ADDR             0x02
+#define CFG_SYS_SGMII2_PHY_ADDR             0x03
+#define CFG_SYS_SGMII3_PHY_ADDR             0x01
 #endif
 
 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
-#define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
-#define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
+#define CFG_SYS_RGMII1_PHY_ADDR             0x04
+#define CFG_SYS_RGMII2_PHY_ADDR             0x05
 #else
-#define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
+#define CFG_SYS_RGMII1_PHY_ADDR             0x01
+#define CFG_SYS_RGMII2_PHY_ADDR             0x02
 #endif
 
 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 #define CONFIG_VSC9953
 #ifdef CONFIG_TARGET_T1040RDB
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
 #else
-#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
-#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
+#define CFG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
+#define CFG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
 #endif
 #endif
 #endif
@@ -409,7 +409,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 
 /*
  * Dynamic MTD Partition support with mtdparts