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author | Tom Rini <trini@konsulko.com> | 2019-05-21 07:12:51 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2019-05-21 07:12:51 -0400 |
commit | ffbad25b3221fd1b0cd0aff1128d57fcb279e020 (patch) | |
tree | 26eeb5135dc7184bc29bf40a3bc5a801021b0efe /drivers | |
parent | b9625abe03452f3926afa4308bf25c361af9c0ef (diff) | |
parent | b6a0427554424a9d6bb563cae4f5555487f38caf (diff) | |
download | u-boot-ffbad25b3221fd1b0cd0aff1128d57fcb279e020.zip u-boot-ffbad25b3221fd1b0cd0aff1128d57fcb279e020.tar.gz u-boot-ffbad25b3221fd1b0cd0aff1128d57fcb279e020.tar.bz2 |
Merge tag 'mmc-5-20' of https://github.com/MrVan/u-boot
"Please pull mmc-5-20 for v2019.07, this is to avoid break i.MX53 boot."
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mmc/fsl_esdhc.c | 23 |
1 files changed, 5 insertions, 18 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 1b7de74..377b267 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -621,31 +621,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif + int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; - /* - * For ddr mode, usdhc need to enable DDR mode first, after select - * this DDR mode, usdhc will automatically divide the usdhc clock - */ - if (mmc->ddr_mode) { - writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); - sdhc_clk >>= 1; - } - if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - if (sdhc_clk / 16 > clock) { - for (; pre_div < 256; pre_div *= 2) - if ((sdhc_clk / pre_div) <= (clock * 16)) - break; - } else - pre_div = 1; + while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) + pre_div *= 2; - for (div = 1; div <= 16; div++) - if ((sdhc_clk / (div * pre_div)) <= clock) - break; + while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) + div++; pre_div >>= 1; div -= 1; |