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author | Tom Rini <trini@konsulko.com> | 2019-03-26 23:19:11 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2019-03-26 23:19:11 -0400 |
commit | d32519ac8a4483803975b5aa4ef4f5affe1964bc (patch) | |
tree | c7ffa2fbcbccfd5f1121966d9046b6dfe2659d5b /drivers | |
parent | 2b9b9cdd5f9ae1cbc786ba3c2255a51b3ea4a636 (diff) | |
parent | c453fe3a0513f758c7d0b580307909637eb31c9f (diff) | |
download | u-boot-d32519ac8a4483803975b5aa4ef4f5affe1964bc.zip u-boot-d32519ac8a4483803975b5aa4ef4f5affe1964bc.tar.gz u-boot-d32519ac8a4483803975b5aa4ef4f5affe1964bc.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various fixes for bugs found by u-boot test.py
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/renesas/clk-rcar-gen2.c | 58 | ||||
-rw-r--r-- | drivers/mmc/sh_mmcif.c | 2 | ||||
-rw-r--r-- | drivers/mmc/tmio-common.c | 5 |
3 files changed, 57 insertions, 8 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 6dfd02f..13111b3 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = { { 0, 0 }, }; -static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div) +static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val) { - while ((*table++).val) { - if ((*table).div == div) - return div; + for (;;) { + if (!(*table).div) + return 0xff; + + if ((*table).val == val) + return (*table).div; + + table++; } - return 0xff; } static int gen2_clk_enable(struct clk *clk) @@ -117,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk) case CLK_TYPE_FF: rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; - debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", + debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n", __func__, __LINE__, core->parent, core->mult, core->div, rate); return rate; @@ -202,8 +206,50 @@ static ulong gen2_clk_get_rate(struct clk *clk) return -ENOENT; } +static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate) +{ + struct gen2_clk_priv *priv = dev_get_priv(clk->dev); + struct cpg_mssr_info *info = priv->info; + const struct cpg_core_clk *core; + struct clk parent, pparent; + u32 val; + int ret; + + ret = renesas_clk_get_parent(clk, info, &parent); + if (ret) { + debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } + + if (renesas_clk_is_mod(&parent)) + return 0; + + ret = renesas_clk_get_core(&parent, info, &core); + if (ret) + return ret; + + if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1")) + return 0; + + ret = renesas_clk_get_parent(&parent, info, &pparent); + if (ret) { + debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } + + val = (gen2_clk_get_rate(&pparent) / rate) - 1; + + debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset); + + writel(val, priv->base + core->offset); + + return 0; +} + static ulong gen2_clk_set_rate(struct clk *clk, ulong rate) { + /* Force correct MMC-IF divider configuration if applicable */ + gen2_clk_setup_mmcif_div(clk, rate); return gen2_clk_get_rate(clk); } diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 306daf1..c8875ce 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -696,7 +696,7 @@ static int sh_mmcif_dm_probe(struct udevice *dev) return ret; } - host->clk = clk_get_rate(&sh_mmcif_clk); + host->clk = clk_set_rate(&sh_mmcif_clk, 97500000); plat->cfg.name = dev->name; plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 01d8c2b..812205a 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -783,7 +783,10 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) plat->cfg.f_min = mclk / (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); plat->cfg.f_max = mclk; - plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ + if (quirks & TMIO_SD_CAP_16BIT) + plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */ + else + plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ upriv->mmc = &plat->mmc; |