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| author | Jonathan Liu <net147@gmail.com> | 2023-03-23 21:35:58 +1100 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-04-21 15:16:01 +0800 |
| commit | cf8b415d5cdf11d30eb619e1972ef7a6b4e315e2 (patch) | |
| tree | 3b18a7befc20e046b18d0c2dafbe64c6d80d5c4e /drivers | |
| parent | 88b962f3934a29c825cde579844642d8a57fd212 (diff) | |
| download | u-boot-cf8b415d5cdf11d30eb619e1972ef7a6b4e315e2.zip u-boot-cf8b415d5cdf11d30eb619e1972ef7a6b4e315e2.tar.gz u-boot-cf8b415d5cdf11d30eb619e1972ef7a6b4e315e2.tar.bz2 | |
ram: rk3399: add missing high row detection
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"
U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"
Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3399.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 963a05c..8993245 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -2749,6 +2749,8 @@ static u64 dram_detect_cap(struct dram_info *dram, /* detect cs1 row */ sdram_detect_cs1_row(cap_info, params->base.dramtype); + sdram_detect_high_row(cap_info); + /* detect die bw */ sdram_detect_dbw(cap_info, params->base.dramtype); |