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| author | Jonas Karlman <jonas@kwiboo.se> | 2025-02-09 23:27:55 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2025-02-19 23:26:11 +0800 |
| commit | c4ec920cb9452a59ab054f98debecd41c4f21515 (patch) | |
| tree | bd7e8a3f6e7c2be641b389d2a4c4562e99209b4e /drivers | |
| parent | d5a3fb9ef82a99f3d6498d562691a6a3c84c5528 (diff) | |
| download | u-boot-c4ec920cb9452a59ab054f98debecd41c4f21515.zip u-boot-c4ec920cb9452a59ab054f98debecd41c4f21515.tar.gz u-boot-c4ec920cb9452a59ab054f98debecd41c4f21515.tar.bz2 | |
net: dwc_eth_qos_rockchip: Fix disable of RX/TX delay for RK356x
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/dwc_eth_qos_rockchip.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 9fc8c68..3e10e07 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -46,6 +46,10 @@ struct rockchip_platform_data { #define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) #define GRF_CLR_BIT(nr) (BIT((nr) + 16)) +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev, regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RGMII | - RK3568_GMAC_RXCLK_DLY_ENABLE | - RK3568_GMAC_TXCLK_DLY_ENABLE); + DELAY_ENABLE(RK3568, tx_delay, rx_delay)); return 0; } |