net: mediatek: fix coding style of AN8855 switch driver

This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

1 files changed, 44 insertions, 45 deletions

diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
index 4bd7506..25a98e0 100644
--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
@@ -22,7 +22,7 @@
 #define AN8855_FORCE_MODE_LNK			BIT(31)
 #define AN8855_FORCE_MODE			0xb31593f0
 
-#define AN8855_PORT_CTRL_BASE			(0x10208000)
+#define AN8855_PORT_CTRL_BASE			0x10208000
 #define AN8855_PORT_CTRL_REG(p, r)		(AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r))
 
 #define AN8855_PORTMATRIX_REG(p)		AN8855_PORT_CTRL_REG(p, 0x44)
@@ -46,7 +46,7 @@
 
 #define AN8855_CKGCR				0x10213e1c
 
-#define AN8855_SCU_BASE 			0x10000000
+#define AN8855_SCU_BASE				0x10000000
 #define AN8855_RG_RGMII_TXCK_C			(AN8855_SCU_BASE + 0x1d0)
 #define AN8855_RG_GPIO_LED_MODE			(AN8855_SCU_BASE + 0x0054)
 #define AN8855_RG_GPIO_LED_SEL(i)		(AN8855_SCU_BASE + (0x0058 + ((i) * 4)))
@@ -66,23 +66,23 @@
 #define AN8855_RG_HSGMII_PCS_CTROL_1		(AN8855_HSGMII_CSR_PCS_BASE + 0xa00)
 #define AN8855_RG_AN_SGMII_MODE_FORCE		(AN8855_HSGMII_CSR_PCS_BASE + 0xa24)
 
-#define AN8855_MULTI_SGMII_CSR_BASE 		0x10224000
-#define AN8855_SGMII_STS_CTRL_0 		(AN8855_MULTI_SGMII_CSR_BASE + 0x018)
+#define AN8855_MULTI_SGMII_CSR_BASE		0x10224000
+#define AN8855_SGMII_STS_CTRL_0			(AN8855_MULTI_SGMII_CSR_BASE + 0x018)
 #define AN8855_MSG_RX_CTRL_0			(AN8855_MULTI_SGMII_CSR_BASE + 0x100)
-#define AN8855_MSG_RX_LIK_STS_0 		(AN8855_MULTI_SGMII_CSR_BASE + 0x514)
-#define AN8855_MSG_RX_LIK_STS_2 		(AN8855_MULTI_SGMII_CSR_BASE + 0x51c)
+#define AN8855_MSG_RX_LIK_STS_0			(AN8855_MULTI_SGMII_CSR_BASE + 0x514)
+#define AN8855_MSG_RX_LIK_STS_2			(AN8855_MULTI_SGMII_CSR_BASE + 0x51c)
 #define AN8855_PHY_RX_FORCE_CTRL_0		(AN8855_MULTI_SGMII_CSR_BASE + 0x520)
 
-#define AN8855_XFI_CSR_PCS_BASE 		0x10225000
+#define AN8855_XFI_CSR_PCS_BASE			0x10225000
 #define AN8855_RG_USXGMII_AN_CONTROL_0		(AN8855_XFI_CSR_PCS_BASE + 0xbf8)
 
 #define AN8855_MULTI_PHY_RA_CSR_BASE		0x10226000
-#define AN8855_RG_RATE_ADAPT_CTRL_0 		(AN8855_MULTI_PHY_RA_CSR_BASE + 0x000)
+#define AN8855_RG_RATE_ADAPT_CTRL_0		(AN8855_MULTI_PHY_RA_CSR_BASE + 0x000)
 #define AN8855_RATE_ADP_P0_CTRL_0		(AN8855_MULTI_PHY_RA_CSR_BASE + 0x100)
-#define AN8855_MII_RA_AN_ENABLE 		(AN8855_MULTI_PHY_RA_CSR_BASE + 0x300)
+#define AN8855_MII_RA_AN_ENABLE			(AN8855_MULTI_PHY_RA_CSR_BASE + 0x300)
 
 #define AN8855_QP_DIG_CSR_BASE			0x1022a000
-#define AN8855_QP_CK_RST_CTRL_4 		(AN8855_QP_DIG_CSR_BASE + 0x310)
+#define AN8855_QP_CK_RST_CTRL_4			(AN8855_QP_DIG_CSR_BASE + 0x310)
 #define AN8855_QP_DIG_MODE_CTRL_0		(AN8855_QP_DIG_CSR_BASE + 0x324)
 #define AN8855_QP_DIG_MODE_CTRL_1		(AN8855_QP_DIG_CSR_BASE + 0x330)
 
@@ -90,7 +90,7 @@
 #define AN8855_PON_RXFEDIG_CTRL_0		(AN8855_QP_PMA_TOP_BASE + 0x100)
 #define AN8855_PON_RXFEDIG_CTRL_9		(AN8855_QP_PMA_TOP_BASE + 0x124)
 
-#define AN8855_SS_LCPLL_PWCTL_SETTING_2 	(AN8855_QP_PMA_TOP_BASE + 0x208)
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2		(AN8855_QP_PMA_TOP_BASE + 0x208)
 #define AN8855_SS_LCPLL_TDC_FLT_2		(AN8855_QP_PMA_TOP_BASE + 0x230)
 #define AN8855_SS_LCPLL_TDC_FLT_5		(AN8855_QP_PMA_TOP_BASE + 0x23c)
 #define AN8855_SS_LCPLL_TDC_PCW_1		(AN8855_QP_PMA_TOP_BASE + 0x248)
@@ -101,7 +101,7 @@
 #define AN8855_PLL_CTRL_3			(AN8855_QP_PMA_TOP_BASE + 0x40c)
 #define AN8855_PLL_CTRL_4			(AN8855_QP_PMA_TOP_BASE + 0x410)
 #define AN8855_PLL_CK_CTRL_0			(AN8855_QP_PMA_TOP_BASE + 0x414)
-#define AN8855_RX_DLY_0 			(AN8855_QP_PMA_TOP_BASE + 0x614)
+#define AN8855_RX_DLY_0				(AN8855_QP_PMA_TOP_BASE + 0x614)
 #define AN8855_RX_CTRL_2			(AN8855_QP_PMA_TOP_BASE + 0x630)
 #define AN8855_RX_CTRL_5			(AN8855_QP_PMA_TOP_BASE + 0x63c)
 #define AN8855_RX_CTRL_6			(AN8855_QP_PMA_TOP_BASE + 0x640)
@@ -118,7 +118,7 @@
 #define AN8855_RG_QP_CDR_PR_CKREF_DIV1		(AN8855_QP_ANA_CSR_BASE + 0x18)
 #define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE	(AN8855_QP_ANA_CSR_BASE + 0x1c)
 #define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF	(AN8855_QP_ANA_CSR_BASE + 0x20)
-#define AN8855_RG_QP_TX_MODE_16B_EN 		(AN8855_QP_ANA_CSR_BASE + 0x28)
+#define AN8855_RG_QP_TX_MODE_16B_EN		(AN8855_QP_ANA_CSR_BASE + 0x28)
 #define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL	(AN8855_QP_ANA_CSR_BASE + 0x3c)
 #define AN8855_RG_QP_PLL_SDM_ORD		(AN8855_QP_ANA_CSR_BASE + 0x40)
 
@@ -135,49 +135,49 @@
 #define PHY_SINGLE_LED_ON_DUR(i)		(0x3e9 + ((i) * 2))
 #define PHY_SINGLE_LED_BLK_DUR(i)		(0x3ea + ((i) * 2))
 
-#define PHY_PMA_CTRL				(0x340)
+#define PHY_PMA_CTRL				0x340
 
 #define PHY_DEV1F				0x1f
 
 #define PHY_LED_ON_CTRL(i)			(0x24 + ((i) * 2))
-#define LED_ON_EN				(1 << 15)
-#define LED_ON_POL				(1 << 14)
-#define LED_ON_EVT_MASK				(0x7f)
+#define LED_ON_EN				BIT(15)
+#define LED_ON_POL				BIT(14)
+#define LED_ON_EVT_MASK				0x7f
 
 /* LED ON Event */
-#define LED_ON_EVT_FORCE			(1 << 6)
-#define LED_ON_EVT_LINK_HD			(1 << 5)
-#define LED_ON_EVT_LINK_FD			(1 << 4)
-#define LED_ON_EVT_LINK_DOWN			(1 << 3)
-#define LED_ON_EVT_LINK_10M			(1 << 2)
-#define LED_ON_EVT_LINK_100M			(1 << 1)
-#define LED_ON_EVT_LINK_1000M			(1 << 0)
+#define LED_ON_EVT_FORCE			BIT(6)
+#define LED_ON_EVT_LINK_HD			BIT(5)
+#define LED_ON_EVT_LINK_FD			BIT(4)
+#define LED_ON_EVT_LINK_DOWN			BIT(3)
+#define LED_ON_EVT_LINK_10M			BIT(2)
+#define LED_ON_EVT_LINK_100M			BIT(1)
+#define LED_ON_EVT_LINK_1000M			BIT(0)
 
 #define PHY_LED_BLK_CTRL(i)			(0x25 + ((i) * 2))
-#define LED_BLK_EVT_MASK			(0x3ff)
+#define LED_BLK_EVT_MASK			0x3ff
 /* LED Blinking Event */
-#define LED_BLK_EVT_FORCE			(1 << 9)
-#define LED_BLK_EVT_10M_RX_ACT			(1 << 5)
-#define LED_BLK_EVT_10M_TX_ACT			(1 << 4)
-#define LED_BLK_EVT_100M_RX_ACT			(1 << 3)
-#define LED_BLK_EVT_100M_TX_ACT			(1 << 2)
-#define LED_BLK_EVT_1000M_RX_ACT		(1 << 1)
-#define LED_BLK_EVT_1000M_TX_ACT		(1 << 0)
+#define LED_BLK_EVT_FORCE			BIT(9)
+#define LED_BLK_EVT_10M_RX_ACT			BIT(5)
+#define LED_BLK_EVT_10M_TX_ACT			BIT(4)
+#define LED_BLK_EVT_100M_RX_ACT			BIT(3)
+#define LED_BLK_EVT_100M_TX_ACT			BIT(2)
+#define LED_BLK_EVT_1000M_RX_ACT		BIT(1)
+#define LED_BLK_EVT_1000M_TX_ACT		BIT(0)
 
 #define PHY_LED_BCR				(0x21)
-#define LED_BCR_EXT_CTRL			(1 << 15)
-#define LED_BCR_CLK_EN				(1 << 3)
-#define LED_BCR_TIME_TEST			(1 << 2)
-#define LED_BCR_MODE_MASK			(3)
-#define LED_BCR_MODE_DISABLE			(0)
+#define LED_BCR_EXT_CTRL			BIT(15)
+#define LED_BCR_CLK_EN				BIT(3)
+#define LED_BCR_TIME_TEST			BIT(2)
+#define LED_BCR_MODE_MASK			3
+#define LED_BCR_MODE_DISABLE			0
 
-#define PHY_LED_ON_DUR				(0x22)
-#define LED_ON_DUR_MASK				(0xffff)
+#define PHY_LED_ON_DUR				0x22
+#define LED_ON_DUR_MASK				0xffff
 
-#define PHY_LED_BLK_DUR				(0x23)
-#define LED_BLK_DUR_MASK			(0xffff)
+#define PHY_LED_BLK_DUR				0x23
+#define LED_BLK_DUR_MASK			0xffff
 
-#define PHY_LED_BLINK_DUR_CTRL			(0x720)
+#define PHY_LED_BLINK_DUR_CTRL			0x720
 
 /* Definition of LED */
 #define LED_ON_EVENT	(LED_ON_EVT_LINK_1000M | \
@@ -993,7 +993,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv)
 
 	/* Switch soft reset */
 	an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST);
-	udelay(100000);
+	mdelay(100);
 
 	an8855_reg_read(priv, AN8855_PKG_SEL, &val);
 	if ((val & 0x7) == PAG_SEL_AN8855H) {
@@ -1003,8 +1003,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv)
 		/* Invert for LED activity change */
 		an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val);
 		for (id = 0; id < ARRAY_SIZE(led_cfg); id++) {
-			if ((led_cfg[id].pol == LED_HIGH) &&
-			    (led_cfg[id].en == 1))
+			if (led_cfg[id].pol == LED_HIGH && led_cfg[id].en == 1)
 				val |= 0x1 << id;
 		}
 		an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1));