Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
  arm: jadecpu: Readd MACH_TYPE_JADECPU
  at91: defined mach-types for otc570 board in board config file
  at91: defined mach-types for meesc board in board config file
  mx31pdk: Enable D and I caches
  ehci-mxc: remove incorrect comment
  README: Fix supported i.MX SoC list for CONFIG_MXC_SPI
  mx53: Turn off child clocks before reconfigure perclk_root
  qong: enable support for compressed images
  imx: imx31_phycore.h: fix checkpatch warnings
  vision2: Remove unused get_board_rev function
  mx53smd: Remove unused get_board_rev function
  mx53ard: Remove unused get_board_rev function
  mx53evk: Remove unused get_board_rev function
  mx53evk: Add RTC support
  mx53loco: Remove unused get_board_rev function
  mx53evk: Remove unneeded '1' from mx53evk.h
  OMAP3: mvblx: Initial support for mvBlueLYNX-X
  ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE
  omap3: mem: Move comments next to definitions
  omap3: mem: Clean-up whitespaces
  omap3: mem: Define and use common macros
  Davinci: ea20: added PREBOOT to configuration
  Davinci: ea20: added I2C support
  Davinci: ea20: added video support
  VIDEO: davinci: add framebuffer to da8xx
  ARM: Davinci: added missing registers to hardware.h
  Davinci: ea20: add gpios for LCD backlight control
  Davinci: ea20: add gpio for keeping power on in board_late_init
  Davinci: ea20: Add default U-Boot environment
  Davinci: ea20: Add early init to get early output from console
  Davinci: ea20: Add NAND support
  Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
  Davinci: ea20: set console on UART0
  arm, davinci: add cam_enc_4xx support
  arm926ejs, davinci: add missing spi defines for dm365
  arm926ejs, davinci: add cpuinfo for dm365
  arm, davinci: add lowlevel function for dm365 soc
  arm, davinci: add header files for dm365
  spl, nand: add 4bit HW ecc oob first nand_read_page function
  arm, davinci: add support for new spl framework
  spl: add option for adding post memory test to the SPL framework
  net, davinci_emac: make clock divider in MDIO control register configurable
  arm, usb, davinci: make USBPHY_CTL register configurable
  usb, davinci: add enable_vbus() weak function
  omap3evm: fix errors caused by multiple definitions
  omap3evm: Add (quick) configuration for NAND only
  omap3evm: Add (quick) configuration for MMC/SD only
  omap3evm: move common config options to new file
  omap3evm: Prepare to split configuration
  omap3evm: Reorder related config options
  omap/spl: actually enable the console
  davinci_emac: compilation fix, phy is array now
  omap3evm: Set environment variable 'ethaddr'
  arm, arm926: fix missing symbols in NAND_SPL mode
  arm, davinci: Add function lpsc_syncreset()
  arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
  arm/km: portl2 environment address update to P1B
  arm/km: adapt bootcounter evaluation
  arm/km: enable jffs2 cmds
  arm/km: trigger reconfiguration for the Xilinx FPGA
  arm/km: add boardid and hwkey to kernel command line
  ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards
  netspace_v2: enable I2C EEPROM support
  netspace_v2: fix SDRAM configuration
  armada100: define CONFIG_SYS_CACHELINE_SIZE
  pantheon: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: drop empty asm-offsets.s file
  arm/km/mgcoge3un: enhance "waitforne" feature
  arm/km: add variable waitforne to mgcoge3un
  gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
  ARM: dreamplug: fix compilation
  ARM: DockStar: fix compilation
  ARM: netspace_v2: fix warnings
  am335x: Drop board_sysinfo struct
  am335x: Temporarily add MACH_TYPE define
  misc:pmic:samsung Enable PMIC driver at C210 Universal target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target
  smdkv310: use macro for mmc data read function address
  smdkv310: use spl framework for mmc spl
  SMDKV310: use get_ram_size() to validate dram size
  SMDKV310: Initialize board id using CONFIG_MACH_TYPE
  ORIGEN : use absolute paths and fix tool naming
  ORIGEN : enable device tree support
  MX25: tx25: Fix building due to missing MACH_TYPE
  mx31: Add board support for HALE TT-01
  mx31: add ESD control registers
  mx31: define pins and init for UART2 and CSPI3
  MX35: add support for flea3 board
  MX51: vision2: add MACH_TYPE in config file
  vision2: Remove unused header file
  mx51evk: Remove unused get_board_rev function
  mx51evk: Remove unneeded '1' from mx51evk.h
  I2C: Fix mxc_i2c.c problem on imx31_phycore
  mx35pdk: Add RTC support
  mx51evk: Use GPIO API for configuring the IOMUX
  mx51evk: Add RTC support
  rtc: Make mc13783-rtc driver generic
  qong: remove unneeded IOMUX settings
  qong: Use mx31_set_gpr to setup USBH2 pins
  mx31: Introduce mx31_set_gpr function
  mx31pdk: Add MC13783 PMIC support
  qong: remove unneeded "1" from qong.h
  misc: pmic: fix regression in pmic_fsl.c (SPI)
  mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME
  MX35: Drop unnecessary prototypes from imx-regs.h
  I2C: added I2C-2 and I2C-3 to MX35
  MX35: factorize common assembly code
  MX35: add reset cause as provided by other i.MX
  MX35: add pins definition for UART3
  MX35: added ESDC structure to imx-regs

15 files changed, 1008 insertions, 26 deletions

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 2869d7c..c88ac7c 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -37,6 +37,7 @@
 
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <i2c.h>
 
 struct mxc_i2c_regs {
 	uint32_t	iadr;
@@ -73,6 +74,10 @@ struct mxc_i2c_regs {
 #define I2C_BASE        I2C2_BASE_ADDR
 #elif defined(CONFIG_SYS_I2C_MX35_PORT1)
 #define I2C_BASE	I2C_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
+#define I2C_BASE	I2C2_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
+#define I2C_BASE	I2C3_BASE_ADDR
 #else
 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
 #endif
@@ -95,16 +100,14 @@ static u16 i2c_clk_div[50][2] = {
 	{ 3072,	0x1E }, { 3840,	0x1F }
 };
 
-static u8 clk_div;
-
 /*
  * Calculate and set proper clock divider
  */
-static void i2c_imx_set_clk(unsigned int rate)
+static uint8_t i2c_imx_get_clk(unsigned int rate)
 {
-	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int i2c_clk_rate;
 	unsigned int div;
+	u8 clk_div;
 
 #if defined(CONFIG_MX31)
 	struct clock_control_regs *sc_regs =
@@ -127,7 +130,7 @@ static void i2c_imx_set_clk(unsigned int rate)
 			;
 
 	/* Store divider value */
-	writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr);
+	return clk_div;
 }
 
 /*
@@ -146,7 +149,13 @@ void i2c_reset(void)
  */
 void i2c_init(int speed, int unused)
 {
-	i2c_imx_set_clk(speed);
+	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+	u8 clk_idx = i2c_imx_get_clk(speed);
+	u8 idx = i2c_clk_div[clk_idx][1];
+
+	/* Store divider value */
+	writeb(idx, &i2c_regs->ifdr);
+
 	i2c_reset();
 }
 
@@ -164,6 +173,13 @@ int i2c_set_bus_speed(unsigned int speed)
  */
 unsigned int i2c_get_bus_speed(void)
 {
+	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+	u8 clk_idx = readb(&i2c_regs->ifdr);
+	u8 clk_div;
+
+	for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
+		;
+
 	return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
 }
 
@@ -232,8 +248,12 @@ int i2c_imx_start(void)
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int temp = 0;
 	int result;
+	int speed = i2c_get_bus_speed();
+	u8 clk_idx = i2c_imx_get_clk(speed);
+	u8 idx = i2c_clk_div[clk_idx][1];
 
-	writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr);
+	/* Store divider value */
+	writeb(idx, &i2c_regs->ifdr);
 
 	/* Enable I2C controller */
 	writeb(0, &i2c_regs->i2sr);
@@ -306,11 +326,10 @@ int i2c_imx_set_chip_addr(uchar chip, int read)
 int i2c_imx_set_reg_addr(uint addr, int alen)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-	int ret;
-	int i;
+	int ret = 0;
 
-	for (i = 0; i < (8 * alen); i += 8) {
-		writeb((addr >> i) & 0xff, &i2c_regs->i2dr);
+	while (alen--) {
+		writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
 
 		ret = i2c_imx_trx_complete();
 		if (ret)
diff --git a/drivers/misc/pmic_fsl.c b/drivers/misc/pmic_fsl.c
index b6e809a..0ff75ed 100644
--- a/drivers/misc/pmic_fsl.c
+++ b/drivers/misc/pmic_fsl.c
@@ -29,10 +29,7 @@
 #if defined(CONFIG_PMIC_SPI)
 static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
 {
-	if ((val == NULL) && (write))
-		return *val & ~(1 << 31);
-	else
-		return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
+	return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
 }
 #endif
 
diff --git a/drivers/misc/pmic_spi.c b/drivers/misc/pmic_spi.c
index ff35377..5a0dd22 100644
--- a/drivers/misc/pmic_spi.c
+++ b/drivers/misc/pmic_spi.c
@@ -76,8 +76,7 @@ static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
 	}
 
 	if (write) {
-		pmic_tx = p->hw.spi.prepare_tx(0, NULL, write);
-		pmic_tx &= ~(1 << 31);
+		pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
 		tmp = cpu_to_be32(pmic_tx);
 		if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
 			pmic_spi_flags)) {
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1eeba5c..28bd350 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -30,6 +30,9 @@ ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_NAND_SIMPLE
 COBJS-y += nand_spl_simple.o
 endif
+ifdef CONFIG_SPL_NAND_LOAD
+COBJS-y	+= nand_spl_load.o
+endif
 else
 COBJS-y += nand.o
 COBJS-y += nand_bbt.o
diff --git a/drivers/mtd/nand/nand_spl_load.c b/drivers/mtd/nand/nand_spl_load.c
new file mode 100644
index 0000000..ae8d5ac
--- /dev/null
+++ b/drivers/mtd/nand/nand_spl_load.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+	int ret;
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	/*
+	 * Load U-Boot image from NAND into RAM
+	 */
+	ret =  nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			CONFIG_SYS_NAND_U_BOOT_SIZE,
+		(void *)CONFIG_SYS_NAND_U_BOOT_DST);
+
+#ifdef CONFIG_NAND_ENV_DST
+	ret =  nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+		(void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+	ret =  nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+		(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	(*uboot)();
+}
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 71491d4..e5003e6 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -140,6 +140,47 @@ static int nand_is_bad_block(int block)
 	return 0;
 }
 
+#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	struct nand_chip *this = mtd.priv;
+	u_char *ecc_calc;
+	u_char *ecc_code;
+	u_char *oob_data;
+	int i;
+	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
+	uint8_t *p = dst;
+	int stat;
+
+	/*
+	 * No malloc available for now, just use some temporary locations
+	 * in SDRAM
+	 */
+	ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
+	ecc_code = ecc_calc + 0x100;
+	oob_data = ecc_calc + 0x200;
+
+	nand_command(block, page, 0, NAND_CMD_READOOB);
+	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	nand_command(block, page, 0, NAND_CMD_READ0);
+
+	/* Pick the ECC bytes out of the oob data */
+	for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
+		ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		this->ecc.hwctl(&mtd, NAND_ECC_READ);
+		this->read_buf(&mtd, p, eccsize);
+		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+		stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+	}
+
+	return 0;
+}
+#else
 static int nand_read_page(int block, int page, void *dst)
 {
 	struct nand_chip *this = mtd.priv;
@@ -186,6 +227,7 @@ static int nand_read_page(int block, int page, void *dst)
 
 	return 0;
 }
+#endif
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
@@ -230,7 +272,6 @@ void nand_init(void)
 	mtd.priv = &nand_chip;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
-	nand_chip.options = 0;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 7dacb23..fa31159 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -53,6 +53,11 @@ unsigned int	emac_dbg = 0;
 #define emac_gigabit_enable(phy_addr)	/* no gigabit to enable */
 #endif
 
+#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
+#define CONFIG_SYS_EMAC_TI_CLKDIV	((EMAC_MDIO_BUS_FREQ / \
+		EMAC_MDIO_CLOCK_FREQ) - 1)
+#endif
+
 static void davinci_eth_mdio_enable(void);
 
 static int gen_init_phy(int phy_addr);
@@ -131,7 +136,7 @@ static void davinci_eth_mdio_enable(void)
 {
 	u_int32_t	clkdiv;
 
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+	clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 
 	writel((clkdiv & 0xff) |
 	       MDIO_CONTROL_ENABLE |
@@ -473,7 +478,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 #endif
 
 	/* Init MDIO & get link state */
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+	clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 	writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 	       &adap_mdio->CONTROL);
 
@@ -809,7 +814,7 @@ int davinci_emac_initialize(void)
 			phy[i].auto_negotiate = gen_auto_negotiate;
 		}
 
-		debug("Ethernet PHY: %s\n", phy.name);
+		debug("Ethernet PHY: %s\n", phy[i].name);
 
 		miiphy_register(phy[i].name, davinci_mii_phy_read,
 						davinci_mii_phy_write);
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index c7f7446..fd13428 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -37,6 +37,7 @@
 #include <asm/types.h>
 #include <asm/system.h>
 #include <asm/byteorder.h>
+#include <asm/arch/cpu.h>
 
 #if defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index df440c6..a16f590 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -50,7 +50,7 @@ COBJS-$(CONFIG_RTC_M41T62) += m41t62.o
 COBJS-$(CONFIG_RTC_M41T94) += m41t94.o
 COBJS-$(CONFIG_RTC_M48T35A) += m48t35ax.o
 COBJS-$(CONFIG_RTC_MAX6900) += max6900.o
-COBJS-$(CONFIG_RTC_MC13783) += mc13783-rtc.o
+COBJS-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
 COBJS-$(CONFIG_RTC_MC146818) += mc146818.o
 COBJS-$(CONFIG_MCFRTC) += mcfrtc.o
 COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o
diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13xxx-rtc.c
index 70ea8a1..70ea8a1 100644
--- a/drivers/rtc/mc13783-rtc.c
+++ b/drivers/rtc/mc13xxx-rtc.c
diff --git a/drivers/rtc/mvrtc.c b/drivers/rtc/mvrtc.c
index ccc573a..edc1f4f 100644
--- a/drivers/rtc/mvrtc.c
+++ b/drivers/rtc/mvrtc.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <command.h>
 #include <rtc.h>
+#include <asm/io.h>
 #include "mvrtc.h"
 
 /* This RTC does not support century, so we assume 20 */
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..f403d49 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -120,7 +120,6 @@ int ehci_hcd_init(void)
 
 	udelay(80);
 
-	/* Take USB2 */
 	ehci = (struct usb_ehci *)(IMX_USB_BASE +
 		(0x200 * CONFIG_MXC_USB_PORT));
 	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index f56f2df..359c635 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -26,6 +26,10 @@
 #include "davinci.h"
 #include <asm/arch/hardware.h>
 
+#if !defined(CONFIG_DV_USBPHY_CTL)
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN)
+#endif
+
 /* MUSB platform configuration */
 struct musb_config musb_cfg = {
 	.regs		= (struct musb_regs *)MENTOR_USB0_BASE,
@@ -50,7 +54,7 @@ static u8 phy_on(void)
 	writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN |
 			USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
 #else
-	writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
+	writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR);
 #endif
 	timeout = musb_cfg.timeout;
 
@@ -78,6 +82,17 @@ static void phy_off(void)
 	writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR);
 }
 
+void __enable_vbus(void)
+{
+	/*
+	 *  nothing to do, vbus is handled through the cpu.
+	 *  Define this function in board code, if it is
+	 *  different on your board.
+	 */
+}
+void  enable_vbus(void)
+	__attribute__((weak, alias("__enable_vbus")));
+
 /*
  * This function performs Davinci platform specific initialization for usb0.
  */
@@ -86,9 +101,8 @@ int musb_platform_init(void)
 	u32  revision;
 
 	/* enable USB VBUS */
-#ifndef DAVINCI_DM365EVM
 	enable_vbus();
-#endif
+
 	/* start the on-chip USB phy and its pll */
 	if (!phy_on())
 		return -1;
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ecc1896..6252f6a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
+COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
new file mode 100644
index 0000000..bca9fb5
--- /dev/null
+++ b/drivers/video/da8xx-fb.c
@@ -0,0 +1,846 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "videomodes.h"
+#include <asm/arch/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME1		(1 << 9)
+#define LCD_END_OF_FRAME0		(1 << 8)
+#define LCD_PL_LOAD_DONE		(1 << 6)
+#define LCD_FIFO_UNDERFLOW		(1 << 5)
+#define LCD_SYNC_LOST			(1 << 2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x)		((x) << 4)
+#define LCD_DMA_BURST_1			0x0
+#define LCD_DMA_BURST_2			0x1
+#define LCD_DMA_BURST_4			0x2
+#define LCD_DMA_BURST_8			0x3
+#define LCD_DMA_BURST_16		0x4
+#define LCD_END_OF_FRAME_INT_ENA	(1 << 2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE	(1 << 0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x)		((x) << 8)
+#define LCD_RASTER_MODE			0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
+#define PALETTE_AND_DATA		0x00
+#define PALETTE_ONLY			0x01
+#define DATA_ONLY			0x02
+
+#define LCD_MONO_8BIT_MODE		(1 << 9)
+#define LCD_RASTER_ORDER		(1 << 8)
+#define LCD_TFT_MODE			(1 << 7)
+#define LCD_UNDERFLOW_INT_ENA		(1 << 6)
+#define LCD_PL_ENABLE			(1 << 4)
+#define LCD_MONOCHROME_MODE		(1 << 1)
+#define LCD_RASTER_ENABLE		(1 << 0)
+#define LCD_TFT_ALT_ENABLE		(1 << 23)
+#define LCD_STN_565_ENABLE		(1 << 24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
+#define LCD_SYNC_CTRL				(1 << 25)
+#define LCD_SYNC_EDGE				(1 << 24)
+#define LCD_INVERT_PIXEL_CLOCK			(1 << 22)
+#define LCD_INVERT_LINE_CLOCK			(1 << 21)
+#define LCD_INVERT_FRAME_CLOCK			(1 << 20)
+
+/* LCD Block */
+struct da8xx_lcd_regs {
+	u32	revid;
+	u32	ctrl;
+	u32	stat;
+	u32	lidd_ctrl;
+	u32	lidd_cs0_conf;
+	u32	lidd_cs0_addr;
+	u32	lidd_cs0_data;
+	u32	lidd_cs1_conf;
+	u32	lidd_cs1_addr;
+	u32	lidd_cs1_data;
+	u32	raster_ctrl;
+	u32	raster_timing_0;
+	u32	raster_timing_1;
+	u32	raster_timing_2;
+	u32	raster_subpanel;
+	u32	reserved;
+	u32	dma_ctrl;
+	u32	dma_frm_buf_base_addr_0;
+	u32	dma_frm_buf_ceiling_addr_0;
+	u32	dma_frm_buf_base_addr_1;
+	u32	dma_frm_buf_ceiling_addr_1;
+};
+
+#define LCD_NUM_BUFFERS	1
+
+#define WSI_TIMEOUT	50
+#define PALETTE_SIZE	256
+#define LEFT_MARGIN	64
+#define RIGHT_MARGIN	64
+#define UPPER_MARGIN	32
+#define LOWER_MARGIN	32
+
+#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static struct da8xx_lcd_regs *da8xx_fb_reg_base;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* graphics setup */
+static GraphicDevice gpanel;
+static const struct da8xx_panel *lcd_panel;
+static struct fb_info *da8xx_fb_info;
+static int bits_x_pixel;
+
+static inline unsigned int lcdc_read(u32 *addr)
+{
+	return (unsigned int)readl(addr);
+}
+
+static inline void lcdc_write(unsigned int val, u32 *addr)
+{
+	writel(val, addr);
+}
+
+struct da8xx_fb_par {
+	u32			 p_palette_base;
+	unsigned char *v_palette_base;
+	dma_addr_t		vram_phys;
+	unsigned long		vram_size;
+	void			*vram_virt;
+	unsigned int		dma_start;
+	unsigned int		dma_end;
+	struct clk *lcdc_clk;
+	int irq;
+	unsigned short pseudo_palette[16];
+	unsigned int palette_sz;
+	unsigned int pxl_clk;
+	int blank;
+	int			vsync_flag;
+	int			vsync_timeout;
+};
+
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var = {
+	.xoffset = 0,
+	.yoffset = 0,
+	.transp = {0, 0, 0},
+	.nonstd = 0,
+	.activate = 0,
+	.height = -1,
+	.width = -1,
+	.pixclock = 46666,	/* 46us - AUO display */
+	.accel_flags = 0,
+	.left_margin = LEFT_MARGIN,
+	.right_margin = RIGHT_MARGIN,
+	.upper_margin = UPPER_MARGIN,
+	.lower_margin = LOWER_MARGIN,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix = {
+	.id = "DA8xx FB Drv",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.type_aux = 0,
+	.visual = FB_VISUAL_PSEUDOCOLOR,
+	.xpanstep = 0,
+	.ypanstep = 1,
+	.ywrapstep = 0,
+	.accel = FB_ACCEL_NONE
+};
+
+static const struct display_panel disp_panel = {
+	QVGA,
+	16,
+	16,
+	COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+	&disp_panel,
+	.ac_bias		= 255,
+	.ac_bias_intrpt		= 0,
+	.dma_burst_sz		= 16,
+	.bpp			= 16,
+	.fdd			= 255,
+	.tft_alt_mode		= 0,
+	.stn_565_mode		= 0,
+	.mono_8bit_mode		= 0,
+	.invert_line_clock	= 1,
+	.invert_frm_clock	= 1,
+	.sync_edge		= 0,
+	.sync_ctrl		= 1,
+	.raster_order		= 0,
+};
+
+/* Enable the Raster Engine of the LCD Controller */
+static inline void lcd_enable_raster(void)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+	if (!(reg & LCD_RASTER_ENABLE))
+		lcdc_write(reg | LCD_RASTER_ENABLE,
+			&da8xx_fb_reg_base->raster_ctrl);
+}
+
+/* Disable the Raster Engine of the LCD Controller */
+static inline void lcd_disable_raster(void)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+	if (reg & LCD_RASTER_ENABLE)
+		lcdc_write(reg & ~LCD_RASTER_ENABLE,
+			&da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+	u32 start;
+	u32 end;
+	u32 reg_ras;
+	u32 reg_dma;
+
+	/* init reg to clear PLM (loading mode) fields */
+	reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+	reg_ras &= ~(3 << 20);
+
+	reg_dma  = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+
+	if (load_mode == LOAD_DATA) {
+		start    = par->dma_start;
+		end      = par->dma_end;
+
+		reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
+		reg_dma |= LCD_END_OF_FRAME_INT_ENA;
+
+#if (LCD_NUM_BUFFERS == 2)
+		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#else
+		reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+		lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+		lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#endif
+
+	} else if (load_mode == LOAD_PALETTE) {
+		start    = par->p_palette_base;
+		end      = start + par->palette_sz - 1;
+
+		reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+		reg_ras |= LCD_PL_ENABLE;
+
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+	}
+
+	lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
+	lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+	/*
+	 * The Raster enable bit must be set after all other control fields are
+	 * set.
+	 */
+	lcd_enable_raster();
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+	switch (burst_size) {
+	case 1:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+		break;
+	case 2:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+		break;
+	case 4:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+		break;
+	case 8:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+		break;
+	case 16:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+		break;
+	default:
+		return -EINVAL;
+	}
+	lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
+
+	return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+	u32 reg;
+
+	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
+	reg |= LCD_AC_BIAS_FREQUENCY(period) |
+		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
+						LCD_MONO_8BIT_MODE |
+						LCD_MONOCHROME_MODE);
+
+	switch (cfg->p_disp_panel->panel_shade) {
+	case MONOCHROME:
+		reg |= LCD_MONOCHROME_MODE;
+		if (cfg->mono_8bit_mode)
+			reg |= LCD_MONO_8BIT_MODE;
+		break;
+	case COLOR_ACTIVE:
+		reg |= LCD_TFT_MODE;
+		if (cfg->tft_alt_mode)
+			reg |= LCD_TFT_ALT_ENABLE;
+		break;
+
+	case COLOR_PASSIVE:
+		if (cfg->stn_565_mode)
+			reg |= LCD_STN_565_ENABLE;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* enable additional interrupts here */
+	reg |= LCD_UNDERFLOW_INT_ENA;
+
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+
+	if (cfg->sync_ctrl)
+		reg |= LCD_SYNC_CTRL;
+	else
+		reg &= ~LCD_SYNC_CTRL;
+
+	if (cfg->sync_edge)
+		reg |= LCD_SYNC_EDGE;
+	else
+		reg &= ~LCD_SYNC_EDGE;
+
+	if (cfg->invert_line_clock)
+		reg |= LCD_INVERT_LINE_CLOCK;
+	else
+		reg &= ~LCD_INVERT_LINE_CLOCK;
+
+	if (cfg->invert_frm_clock)
+		reg |= LCD_INVERT_FRAME_CLOCK;
+	else
+		reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+
+	return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+		u32 bpp, u32 raster_order)
+{
+	u32 reg;
+
+	/* Set the Panel Width */
+	/* Pixels per line = (PPL + 1)*16 */
+	/*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+	width &= 0x3f0;
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
+	reg &= 0xfffffc00;
+	reg |= ((width >> 4) - 1) << 4;
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+
+	/* Set the Panel Height */
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
+	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+
+	/* Set the Raster Order of the Frame Buffer */
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
+	if (raster_order)
+		reg |= LCD_RASTER_ORDER;
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+	switch (bpp) {
+	case 1:
+	case 2:
+	case 4:
+	case 16:
+		par->palette_sz = 16 * 2;
+		break;
+
+	case 8:
+		par->palette_sz = 256 * 2;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			      unsigned blue, unsigned transp,
+			      struct fb_info *info)
+{
+	struct da8xx_fb_par *par = info->par;
+	unsigned short *palette = (unsigned short *) par->v_palette_base;
+	u_short pal;
+	int update_hw = 0;
+
+	if (regno > 255)
+		return 1;
+
+	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+		return 1;
+
+	if (info->var.bits_per_pixel == 8) {
+		red >>= 4;
+		green >>= 8;
+		blue >>= 12;
+
+		pal = (red & 0x0f00);
+		pal |= (green & 0x00f0);
+		pal |= (blue & 0x000f);
+
+		if (palette[regno] != pal) {
+			update_hw = 1;
+			palette[regno] = pal;
+		}
+	} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+		red >>= (16 - info->var.red.length);
+		red <<= info->var.red.offset;
+
+		green >>= (16 - info->var.green.length);
+		green <<= info->var.green.offset;
+
+		blue >>= (16 - info->var.blue.length);
+		blue <<= info->var.blue.offset;
+
+		par->pseudo_palette[regno] = red | green | blue;
+
+		if (palette[0] != 0x4000) {
+			update_hw = 1;
+			palette[0] = 0x4000;
+		}
+	}
+
+	/* Update the palette in the h/w as needed. */
+	if (update_hw)
+		lcd_blit(LOAD_PALETTE, par);
+
+	return 0;
+}
+
+static void lcd_reset(struct da8xx_fb_par *par)
+{
+	/* Disable the Raster if previously Enabled */
+	lcd_disable_raster();
+
+	/* DMA has to be disabled */
+	lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
+	lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+{
+	unsigned int lcd_clk, div;
+
+	/* Get clock from sysclk2 */
+	lcd_clk = clk_get(2);
+
+	div = lcd_clk / par->pxl_clk;
+	debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
+		lcd_clk, div, par->pxl_clk);
+
+	/* Configure the LCD clock divisor. */
+	lcdc_write(LCD_CLK_DIVISOR(div) |
+			(LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+		const struct da8xx_panel *panel)
+{
+	u32 bpp;
+	int ret = 0;
+
+	lcd_reset(par);
+
+	/* Calculate the divider */
+	lcd_calc_clk_divider(par);
+
+	if (panel->invert_pxl_clk)
+		lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
+			LCD_INVERT_PIXEL_CLOCK),
+			 &da8xx_fb_reg_base->raster_timing_2);
+	else
+		lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
+			~LCD_INVERT_PIXEL_CLOCK),
+			&da8xx_fb_reg_base->raster_timing_2);
+
+	/* Configure the DMA burst size. */
+	ret = lcd_cfg_dma(cfg->dma_burst_sz);
+	if (ret < 0)
+		return ret;
+
+	/* Configure the AC bias properties. */
+	lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+	/* Configure the vertical and horizontal sync properties. */
+	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+	/* Configure for disply */
+	ret = lcd_cfg_display(cfg);
+	if (ret < 0)
+		return ret;
+
+	if (QVGA != cfg->p_disp_panel->panel_type)
+		return -EINVAL;
+
+	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+	    cfg->bpp >= cfg->p_disp_panel->min_bpp)
+		bpp = cfg->bpp;
+	else
+		bpp = cfg->p_disp_panel->max_bpp;
+	if (bpp == 12)
+		bpp = 16;
+	ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+				(unsigned int)panel->height, bpp,
+				cfg->raster_order);
+	if (ret < 0)
+		return ret;
+
+	/* Configure FDD */
+	lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
+		       (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
+
+	return 0;
+}
+
+static void lcdc_dma_start(void)
+{
+	struct da8xx_fb_par *par = da8xx_fb_info->par;
+	lcdc_write(par->dma_start,
+		&da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+	lcdc_write(par->dma_end,
+		&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+	lcdc_write(0,
+		&da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+	lcdc_write(0,
+		&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+}
+
+static u32 lcdc_irq_handler(void)
+{
+	struct da8xx_fb_par *par = da8xx_fb_info->par;
+	u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
+	u32 reg_ras;
+
+	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+		debug("LCD_SYNC_LOST\n");
+		lcd_disable_raster();
+		lcdc_write(stat, &da8xx_fb_reg_base->stat);
+		lcd_enable_raster();
+		return LCD_SYNC_LOST;
+	} else if (stat & LCD_PL_LOAD_DONE) {
+		debug("LCD_PL_LOAD_DONE\n");
+		/*
+		 * Must disable raster before changing state of any control bit.
+		 * And also must be disabled before clearing the PL loading
+		 * interrupt via the following write to the status register. If
+		 * this is done after then one gets multiple PL done interrupts.
+		 */
+		lcd_disable_raster();
+
+		lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+		/* Disable PL completion inerrupt */
+		reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+		reg_ras &= ~LCD_PL_ENABLE;
+		lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+		/* Setup and start data loading mode */
+		lcd_blit(LOAD_DATA, par);
+		return LCD_PL_LOAD_DONE;
+	} else {
+		lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+		if (stat & LCD_END_OF_FRAME0)
+			debug("LCD_END_OF_FRAME0\n");
+
+		lcdc_write(par->dma_start,
+			&da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(par->dma_end,
+			&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+		par->vsync_flag = 1;
+		return LCD_END_OF_FRAME0;
+	}
+	return stat;
+}
+
+static u32 wait_for_event(u32 event)
+{
+	u32 timeout = 50000;
+	u32 ret;
+
+	do {
+		ret = lcdc_irq_handler();
+		udelay(1000);
+	} while (!(ret & event));
+
+	if (timeout <= 0) {
+		printf("%s: event %d not hit\n", __func__, event);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+void *video_hw_init(void)
+{
+	struct da8xx_fb_par *par;
+	int ret;
+	u32 size;
+	char *p;
+
+	if (!lcd_panel) {
+		printf("Display not initialized\n");
+		return NULL;
+	}
+	gpanel.winSizeX = lcd_panel->width;
+	gpanel.winSizeY = lcd_panel->height;
+	gpanel.plnSizeX = lcd_panel->width;
+	gpanel.plnSizeY = lcd_panel->height;
+
+	switch (bits_x_pixel) {
+	case 24:
+		gpanel.gdfBytesPP = 4;
+		gpanel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		gpanel.gdfBytesPP = 2;
+		gpanel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	default:
+		gpanel.gdfBytesPP = 1;
+		gpanel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	}
+
+	da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
+
+	debug("Resolution: %dx%d %x\n",
+		gpanel.winSizeX,
+		gpanel.winSizeY,
+		lcd_cfg.bpp);
+
+	size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
+	da8xx_fb_info = malloc(size);
+	debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+
+	if (!da8xx_fb_info) {
+		printf("Memory allocation failed for fb_info\n");
+		return NULL;
+	}
+	memset(da8xx_fb_info, 0, size);
+	p = (char *)da8xx_fb_info;
+	da8xx_fb_info->par = p +  sizeof(struct fb_info);
+	debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
+
+	par = da8xx_fb_info->par;
+	par->pxl_clk = lcd_panel->pxl_clk;
+
+	if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
+		printf("lcd_init failed\n");
+		ret = -EFAULT;
+		goto err_release_fb;
+	}
+
+	/* allocate frame buffer */
+	par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
+	par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
+
+	par->vram_virt = malloc(par->vram_size);
+
+	par->vram_phys = (dma_addr_t) par->vram_virt;
+	debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
+		(unsigned int)par->vram_size,
+		(unsigned int)par->vram_virt);
+	if (!par->vram_virt) {
+		printf("GLCD: malloc for frame buffer failed\n");
+		ret = -EINVAL;
+		goto err_release_fb;
+	}
+
+	gpanel.frameAdrs = (unsigned int)par->vram_virt;
+	da8xx_fb_info->screen_base = (char *) par->vram_virt;
+	da8xx_fb_fix.smem_start	= gpanel.frameAdrs;
+	da8xx_fb_fix.smem_len = par->vram_size;
+	da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
+
+	par->dma_start = par->vram_phys;
+	par->dma_end   = par->dma_start + lcd_panel->height *
+		da8xx_fb_fix.line_length - 1;
+
+	/* allocate palette buffer */
+	par->v_palette_base = malloc(PALETTE_SIZE);
+	if (!par->v_palette_base) {
+		printf("GLCD: malloc for palette buffer failed\n");
+		goto err_release_fb_mem;
+	}
+	memset(par->v_palette_base, 0, PALETTE_SIZE);
+	par->p_palette_base = (unsigned int)par->v_palette_base;
+
+	/* Initialize par */
+	da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+
+	da8xx_fb_var.xres = lcd_panel->width;
+	da8xx_fb_var.xres_virtual = lcd_panel->width;
+
+	da8xx_fb_var.yres         = lcd_panel->height;
+	da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
+
+	da8xx_fb_var.grayscale =
+	    lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+	da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
+
+	da8xx_fb_var.hsync_len = lcd_panel->hsw;
+	da8xx_fb_var.vsync_len = lcd_panel->vsw;
+
+	/* Initialize fbinfo */
+	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+	da8xx_fb_info->fix = da8xx_fb_fix;
+	da8xx_fb_info->var = da8xx_fb_var;
+	da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+	da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
+				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+
+	/* Clear interrupt */
+	memset((void *)par->vram_virt, 0, par->vram_size);
+	lcd_disable_raster();
+	lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+	debug("Palette at 0x%x size %d\n", par->p_palette_base,
+		par->palette_sz);
+	lcdc_dma_start();
+
+	/* Load a default palette */
+	fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
+
+	/* Check that the palette is loaded */
+	wait_for_event(LCD_PL_LOAD_DONE);
+
+	/* Wait until DMA is working */
+	wait_for_event(LCD_END_OF_FRAME0);
+
+	return (void *)&gpanel;
+
+err_release_fb_mem:
+	free(par->vram_virt);
+
+err_release_fb:
+	free(da8xx_fb_info);
+
+	return NULL;
+}
+
+void video_set_lut(unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+		    )
+{
+
+	return;
+}
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
+{
+	lcd_panel = panel;
+	bits_x_pixel = bits_pixel;
+}